Change in coreboot[master]: mb/asrock/h110m: enable ACPI LDN in SuperIO

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Maxim Polyakov (Code Review)

12 Sep 2019 12 Sep '19

10:48 a.m.

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

mb/asrock/h110m: enable ACPI LDN in SuperIO

Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/bootblock.c M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35370/1

diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce205..2fa70e1 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -18,12 +18,25 @@ #include <soc/gpio.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6791d/nct6791d.h> +#include <device/pnp_ops.h> #include "include/gpio.h"

static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + const pnp_devfn_t acpi_dev = PNP_DEV(0x2e, NCT6791D_ACPI); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(acpi_dev); + + pnp_set_logical_device(acpi_dev); + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_write_config(acpi_dev, 0xe4, 0x70); + /* Set Hardware Monitor reset source to LRESET# */ + pnp_write_config(acpi_dev, 0xe7, 0x01); + + nuvoton_pnp_exit_conf_state(acpi_dev); }

static void early_config_gpio(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 8ed3476..038f144 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -365,7 +365,7 @@ device pnp 2e.109 off end # GPIO3 device pnp 2e.209 off end # GPIO4 device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI + device pnp 2e.a on end # ACPI device pnp 2e.b on # HWM, LED # HM base address io 0x60 = 0x0290

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Patrick Rudolph (Code Review)

12 Sep 12 Sep

10:49 a.m.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/bootblock.c:

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... PS1, Line 35: pnp_write_config(acpi_dev, 0xe4, 0x70); why is it done here and not in devicetree.cb?

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 12 Sep 2019 08:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Maxim Polyakov (Code Review)

11:03 a.m.

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 1:

(1 comment)

Thanks for the review

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/bootblock.c:

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... PS1, Line 35: pnp_write_config(acpi_dev, 0xe4, 0x70);

...

why is it done here and not in devicetree. […]

It seemed to me that this should be in bootblock, as it was done in other boards, before all LDNs are enabled in the device tree. But I suppose I could be wrong

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 12 Sep 2019 09:03:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph Gerrit-MessageType: comment

Maxim Polyakov (Code Review)

11:49 a.m.

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35370

to look at the new patch set (#2).

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

mb/asrock/h110m: enable ACPI LDN in SuperIO

Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35370/2

Maxim Polyakov (Code Review)

11:51 a.m.

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/bootblock.c:

https://review.coreboot.org/c/coreboot/+/35370/1/src/mainboard/asrock/h110m/... PS1, Line 35: pnp_write_config(acpi_dev, 0xe4, 0x70);

...

It seemed to me that this should be in bootblock, as it was done in other boards, before all LDNs ar […]

moved to the device tree

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 12 Sep 2019 09:51:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph Comment-In-Reply-To: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-MessageType: comment

Felix Held (Code Review)

3:56 p.m.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35370/2/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/35370/2/src/mainboard/asrock/h110m/... PS2, Line 371: drq the SIO devicetree entries I've seen so far used irq here; not sure if drq is also free of side effects

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 12 Sep 2019 13:56:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Maxim Polyakov (Code Review)

7:08 p.m.

Hello Felix Held, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35370

to look at the new patch set (#3).

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

mb/asrock/h110m: enable ACPI LDN in SuperIO

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35370/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-MessageType: newpatchset

Maxim Polyakov (Code Review)

7:11 p.m.

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35370/2/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/35370/2/src/mainboard/asrock/h110m/... PS2, Line 371: drq

...

the SIO devicetree entries I've seen so far used irq here; not sure if drq is also free of side effe […]

Ok. I will use irq

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 12 Sep 2019 17:11:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held felix-coreboot@felixheld.de Gerrit-MessageType: comment

Felix Held (Code Review)

14 Sep 14 Sep

7:43 a.m.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

Patch Set 3: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Sat, 14 Sep 2019 05:43:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Felix Held (Code Review)

7:47 a.m.

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ......................................................................

mb/asrock/h110m: enable ACPI LDN in SuperIO

Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-)

Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved

diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index eed67b7..9552b10 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -365,7 +365,13 @@ device pnp 2e.109 off end # GPIO3 device pnp 2e.209 off end # GPIO4 device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 io 0x62 = 0

-- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Maxim Polyakov max.senia.poliak@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Patrick Rudolph Gerrit-MessageType: merged

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Felix Held (Code Review)
Maxim Polyakov (Code Review)
Patrick Rudolph (Code Review)