Change in coreboot[master]: drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55025 )

Change subject: drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static
......................................................................

drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static

fsp_temp_ram_exit() function is only getting called by
late_car_teardown() function inside temp_ram_exit.c file.
Hence, make function as static and removed from include/fsp/api.h.

Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc
Signed-off-by: Subrata Banik 
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/temp_ram_exit.c
2 files changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/55025/1

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 8561600..a095b78 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -34,7 +34,6 @@
 /* Main FSP stages */
 void fsp_memory_init(bool s3wake);
 void fsp_silicon_init(void);
-void fsp_temp_ram_exit(void);

/*
  * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c
index 0ef6c5c..5d7cbd4 100644
--- a/src/drivers/intel/fsp2_0/temp_ram_exit.c
+++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c
@@ -7,7 +7,7 @@
 #include <cbfs.h>
 #include <types.h>

-void fsp_temp_ram_exit(void)
+static void fsp_temp_ram_exit(void)
 {
    struct fsp_header hdr;
    uint32_t status;