Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37595 )
Change subject: sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller ......................................................................
sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
Location in hudson_lpc_port80() was called conditionally. Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX() due the change from IO to MMIO using pm_read/write.
Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c 4 files changed, 10 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37595/1
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 6925393..4da030b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -74,8 +74,8 @@ u32 data;
bootblock_southbridge_init(); - hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + hudson_lpc_decode();
if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d85cb2b..84c4299 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h>
#include "hudson.h"
@@ -73,13 +74,6 @@ u8 byte; pci_devfn_t dev;
- /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -92,6 +86,9 @@ pci_devfn_t dev; u32 tmp;
+ /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ec8663d..d16aecc 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -73,11 +73,11 @@ u32 data;
bootblock_southbridge_init(); - hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else enable_acpimmio_decode_pm04(); + hudson_lpc_decode();
if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 56b894c..0e3646b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,6 +22,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h>
#include "hudson.h" #include "pci_devs.h" @@ -106,13 +107,6 @@ u8 byte; pci_devfn_t dev;
- /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -125,6 +119,9 @@ pci_devfn_t dev; u32 tmp;
+ /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37595 )
Change subject: sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37595 )
Change subject: sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller ......................................................................
sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
Location in hudson_lpc_port80() was called conditionally. Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX() due the change from IO to MMIO using pm_read/write.
Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c 4 files changed, 10 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 6925393..4da030b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -74,8 +74,8 @@ u32 data;
bootblock_southbridge_init(); - hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + hudson_lpc_decode();
if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d85cb2b..84c4299 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h>
#include "hudson.h"
@@ -73,13 +74,6 @@ u8 byte; pci_devfn_t dev;
- /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -92,6 +86,9 @@ pci_devfn_t dev; u32 tmp;
+ /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ec8663d..d16aecc 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -73,11 +73,11 @@ u32 data;
bootblock_southbridge_init(); - hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else enable_acpimmio_decode_pm04(); + hudson_lpc_decode();
if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 56b894c..0e3646b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,6 +22,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h>
#include "hudson.h" #include "pci_devs.h" @@ -106,13 +107,6 @@ u8 byte; pci_devfn_t dev;
- /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -125,6 +119,9 @@ pci_devfn_t dev; u32 tmp;
+ /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)