Patch set updated for coreboot: nb/intel/sandybridge: start PEG link training

[Patrick Rudolph]

Patrick Rudolph ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11917

-gerrit

commit bdede31d2726294d08c64d4df761683c0fd55bf9
Author: Patrick Rudolph 
Date:   Thu Oct 15 11:09:15 2015 +0200

nb/intel/sandybridge: start PEG link training

Issue observed:
    The PCIe Root port shows up in GNU/Linux but no device.

Test system:
    * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
    * Lenovo T530 (Intel Core i5-3320M CPU)

Problem description:
    The PEG Root port link training on Ivy Bridge needs to be started by hand.
    (The PEG Root port on Sandy Bridge works out of the box.)

Problem solution:
    The bits are set in early_init to meet PCIe reset timeout of 100msec.
    The bits should be set in PCI device enable function, but this causes the
    PCI enumeration to not detect the card, as it's still booting. Adding
    a fixed delay of 100msec resolves this problem, but this would
    increase boot time.

Tested with:
    * Nvidia NVS 5400M (PCIe2)
    * ATI Radeon HD4780 (PCIe2)
    * Nvidia GeForce 8600 GT (PCIe1)

Untested:
    * PCIe3 devices

Final test results:
    The PEG device shows up under GNU/Linux and can be used without issues.

Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
    Signed-off-by: Patrick Rudolph 
---
 src/northbridge/intel/sandybridge/early_init.c | 42 ++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index b3a829d..7e5ace6 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -148,6 +148,39 @@ static void sandybridge_setup_graphics(void)
    MCHBAR32(0x5418) = reg32;
 }

+static void start_peg_link_training(void)
+{
+	u32 tmp;
+	u32 deven;
+
+	/* skip on SandyBridge */
+	if ((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) &
+			BASE_REV_MASK) != BASE_REV_IVB)
+		return;
+
+	deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+
+	if (deven & DEVEN_PEG10) {
+		tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
+		pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+	}
+
+	if (deven & DEVEN_PEG11) {
+		tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
+		pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+	}
+
+	if (deven & DEVEN_PEG12) {
+		tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
+		pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+	}
+
+	if (deven & DEVEN_PEG60) {
+		tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16);
+		pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5));
+	}
+}
+
 void sandybridge_early_initialization(int chipset_type)
 {
    u32 capid0_a;
@@ -174,6 +207,15 @@ void sandybridge_early_initialization(int chipset_type)
    pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);

sandybridge_setup_graphics();
+
+	/* Write magic value to start PEG link training.
+	 * This should be done in PCI device enumeration, but
+	 * the PCIe specification requires to wait at least 100msec
+	 * after reset for devices to come up.
+	 * As we don't want to increase boot time, enable it early and
+	 * assume the PEG is up as soon as PCI enumeration starts.
+	 * TODO: use time stamps to ensure the timings are met */
+	start_peg_link_training();
 }

void northbridge_romstage_finalize(int s3resume)