[M] Change in coreboot[master]: src/: Cache ISH version in CMOS memory for cold boots

[Dinesh Gehlot (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik.

Hello Kapil Porwal, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/75689?usp=email

to look at the new patch set (#3).

Change subject: src/: Cache ISH version in CMOS memory for cold boots
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src/: Cache ISH version in CMOS memory for cold boots

This patch stores the ISH version in CMOS memory. During a cold reboot,
it updates the CBMEM stored ISH version using the CMOS stored ISH
version.

Previously, the ISH version was updated using CSE during a cold reboot,
which was time-consuming. This change will improve the performance of
cold reboots by approximately ~200ms. Additionally it removes unused
variables for the CBMEM firmware version data structure.

BUG=b:280722061

Signed-off-by: Dinesh Gehlot 
Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224
---
M src/drivers/intel/ish/ish.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_cmos.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/common/block/include/intelblocks/cse_cmos.h
7 files changed, 93 insertions(+), 76 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/75689/3