[M] Change in coreboot[master]: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74293 )

Change subject: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
......................................................................

soc/intel/{adl, cmn}: Send CSE EOP Async CMD early

This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.

Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample whichcauses idle delay while waiting
for EOP response.

The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd.

This patch helps to create ample duration between CSE EOP command
being sent and response being captured.

TEST=Able to boot google/marasov EVT sku to ChromeOS and observed
~30ms of boot time savings (across warm and cold reset scenarios).

Without this patch:

942:before sending EOP to ME                    967,821 (478)
  … 
  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135)
  943:after sending EOP to ME                     1,067,799 (49,861)
  …
  …
  1101:jumping to kernel                          1,144,587 (13,734)

Total Time: 1,144,549

With this patch:

942:before sending EOP to ME                    918,522 (230)
  ...
  16:finished LZMA decompress (ignore for x86)    1,029,476 (12,483)
  943:after sending EOP to ME                     1,033,456 (3,980)
  ...
  ...
  1101:jumping to kernel                          1,111,410 (14,007)

Total Time: 1,111,375

Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/cse/cse.c
2 files changed, 63 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74293/1

diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index e0aa983..25b412e 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -203,7 +203,8 @@
     * current boot sequence) to reduce message response time from CSE hence moving
     * sending EOP to earlier stage.
     */
-	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) {
+	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
+	    CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
    	printk(BIOS_INFO, "Sending EOP early from SoC\n");
    	cse_send_end_of_post();
    }
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 6c4bb73..1aa3454 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1424,22 +1424,23 @@
  */
 static void cse_final(struct device *dev)
 {
-	/* SoC user decided to send EOP late */
-	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+	/*
+	 * SoC user can have two options for sending EOP:
+	 * 1. Choose to send EOP late
+	 * 2. Choose to send EOP cmd asynchronously
+	 *
+	 * In case of sending EOP in asynchronous mode, the EOP command
+	 * has most likely not been completed yet. The finalization steps
+	 * will be run once the EOP command has successfully been completed.
+	 */
+	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) ||
+	    CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
    	return;

/* 1. Send EOP to CSE if not done.*/
    if (CONFIG(SOC_INTEL_CSE_SET_EOP))
    	cse_send_end_of_post();

-	/*
-	 * In asynchronous mode, the EOP command has most likely not been
-	 * completed yet. Finalization steps will be run once the EOP command
-	 * has successfully been completed.
-	 */
-	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
-		return;
-
    if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT))
    	cse_final_ready_to_boot();