Change in coreboot[master]: mb/google/brya: Enable cr50 support

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50567 )

Change subject: mb/google/brya: Enable cr50 support
......................................................................

mb/google/brya: Enable cr50 support

Add Kconfig options and devicetree entries for cr50 TPM.

BUG=b:180017621
TEST=verify (via console) successful cr50 communications in
verstage and payload (depthcharge).

Signed-off-by: Tim Wawrzynczak 
Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
2 files changed, 29 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/50567/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index ca76078..fbda4f7 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -13,6 +13,8 @@
    select HAVE_SPD_IN_CBFS
    select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select MAINBOARD_HAS_TPM2
    select SOC_INTEL_ALDERLAKE

if BOARD_GOOGLE_BASEBOARD_BRYA
@@ -30,6 +32,18 @@
    string
    default "variants/baseboard/devicetree.cb"

+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x3
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 13 # GPE0_DW0_13 (GPP_A13_IRQ)
+
 config OVERRIDE_DEVICETREE
    string
    default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 647ea42..9ced455 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -3,6 +3,13 @@
    	device lapic 0 on end
    end

+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
    register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
@@ -90,6 +97,14 @@
    			device generic 0 on end
    		end
    	end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
    	device ref heci1 on end
    	device ref sata on end
    	device ref pcie_rp5 on