Change in coreboot[master]: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58859 )

Change subject: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure
......................................................................

[RFC] soc/amd/*/cpu: handle mp_init_with_smm failure

When the mp_init_with_smm call returns a failure, coreboot can't just
continue with the initialization and boot process due to the system
being in a bad state. Ignoring the failure here will just cause the boot
process failing elsewhere where it may not be obvious that the failed
multi-processor initialization step was the root cause of that.

I'm not 100% sure if calling do_cold_reset or calling die is the better
option here. Calling do_cold_reset likely here would likely result in a
boot-failure loop, so I call die here.

BUG=b:193809448

Signed-off-by: Felix Held 
Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28
---
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/picasso/cpu.c
M src/soc/amd/stoneyridge/cpu.c
3 files changed, 6 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/58859/1

diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index c3d89bf..103ece0 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -51,9 +51,8 @@

void mp_init_cpus(struct bus *cpu_bus)
 {
-	/* Clear for take-off */
-	/* TODO: Handle mp_init_with_smm failure? */
-	mp_init_with_smm(cpu_bus, &mp_ops);
+	if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+		die("mp_init_with_smm failed. Halting.\n");

/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 9822326..f1f5897 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -55,9 +55,8 @@

void mp_init_cpus(struct bus *cpu_bus)
 {
-	/* Clear for take-off */
-	/* TODO: Handle mp_init_with_smm failure? */
-	mp_init_with_smm(cpu_bus, &mp_ops);
+	if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+		die("mp_init_with_smm failed. Halting.\n");

/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 0655032..5297ee7 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -52,9 +52,8 @@

void mp_init_cpus(struct bus *cpu_bus)
 {
-	/* Clear for take-off */
-	/* TODO: Handle mp_init_with_smm failure? */
-	mp_init_with_smm(cpu_bus, &mp_ops);
+	if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+		die("mp_init_with_smm failed. Halting.\n");

/* The flash is now no longer cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);