nsekar@codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32240
Change subject: qcs405: clock: Update SPI API ......................................................................
qcs405: clock: Update SPI API
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405.
Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain shefjain@codeaurora.org Signed-off-by: Taniya Das tdas@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h 2 files changed, 111 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32240/1
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 31fdc3d..81bf7cb 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -20,7 +20,6 @@ #include <timestamp.h> #include <commonlib/helpers.h> #include <string.h> - #include <soc/clock.h>
#define DIV(div) (div ? (2*div - 1) : 0) @@ -212,11 +211,35 @@ clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); }
-void clock_configure_spi(int blsp, uint32_t hz) +void clock_configure_spi(int blsp, int qup, uint32_t hz) { - struct qcs405_clock *spi_clk = (blsp == 1) ? - (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk - : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + struct qcs405_clock *spi_clk = 0; + + if (blsp == 1) + { + switch (qup) { + case 0: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup0_spi_clk; + break; + case 1: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup1_spi_clk; + break; + case 2: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup2_spi_clk; + break; + case 3: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup3_spi_clk; + break; + case 4: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk; + break; + } + } + else if (blsp == 2) + spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } @@ -231,38 +254,71 @@ clock_disable(&gcc->blsp1_uart2_apps_cbcr); }
-void clock_enable_spi(int blsp) +void clock_enable_spi(int blsp, int qup) { - (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) + { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } + else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); }
-void clock_disable_spi(int blsp) +void clock_disable_spi(int blsp, int qup) { - (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) + { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } + else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + }
void clock_init(void) { - clock_configure_gpll0(); - - clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, - ARRAY_SIZE(uart_cfg)); - - clock_enable(&gcc->blsp1_uart2_apps_cbcr); clock_enable_vote(&gcc->blsp1_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP1_AHB_CLK_ENA);
- clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); - - clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); clock_enable_vote(&gcc->blsp2_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP2_AHB_CLK_ENA); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index d0f307b..8638128 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -21,7 +21,6 @@ #define BLSP2_AHB_CLK_ENA 20 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_800MHZ 1 -#define REG(addr) ((void *)addr)
/** * USB BCR registers @@ -66,28 +65,48 @@ u32 blsp1_bcr; u32 blsp1_sleep_cbcr; u32 blsp1_ahb_cbcr; - u8 _res1[0x3028 - 0x100c]; + struct qcs405_rcg gcc_blsp_uart_sim_rcg; + u8 _res1[0x2000 - 0x1014]; + u32 blsp1_qup1_bcr; + u32 blsp1_qup1_spi_apps_cbcr; + u8 _res2[0x2024 - 0x2008]; + struct qcs405_clock blsp1_qup1_spi_clk; + u8 _res3[0x3008-0x2038]; + u32 blsp1_qup2_bcr; + u32 blsp1_qup2_spi_apps_cbcr; + u8 _res4[0x3014 - 0x3010]; + struct qcs405_clock blsp1_qup2_spi_clk; u32 blsp1_uart2_bcr; u32 blsp1_uart2_apps_cbcr; u32 blsp1_uart2_sim_cbcr; struct qcs405_clock blsp1_uart2_apps_clk; - u8 _res2[0x5018 - 0x3048]; + u8 _res5[0x4018 - 0x3048]; + u32 blsp1_qup3_bcr; + u32 blsp1_qup3_spi_apps_cbcr; + u8 _res6[0x4024 - 0x4020]; + struct qcs405_clock blsp1_qup3_spi_clk; + u8 _res7[0x5018 - 0x4038]; u32 blsp1_qup4_bcr; u32 blsp1_qup4_spi_apps_cbcr; - u8 _res3[0x5024 - 0x5020]; + u8 _res8[0x5024 - 0x5020]; struct qcs405_clock blsp1_qup4_spi_clk; - u8 _res4[0xB000 - 0x5038]; + u8 _res9[0x6020 - 0x5038]; + u32 blsp1_qup0_bcr; + u32 blsp1_qup0_spi_apps_cbcr; + u8 _res10[0x6034 - 0x6028]; + struct qcs405_clock blsp1_qup0_spi_clk; + u8 _res11[0xB000 - 0x6048]; u32 blsp2_bcr; u32 blsp2_sleep_cbcr; u32 blsp2_ahb_cbcr; - u8 _res5[0xC000 - 0xB00C]; + u8 _res12[0xC000 - 0xB00C]; u32 blsp2_qup0_bcr; u32 blsp2_qup0_spi_apps_cbcr; - u8 _res6[0xC024 - 0xC008]; + u8 _res13[0xC024 - 0xC008]; struct qcs405_clock blsp2_qup0_spi_clk; - u8 _res7[0x21000 - 0xC038]; + u8 _res14[0x21000 - 0xC038]; struct qcs405_gpll gpll0; - u8 _res8[0x45004 - 0x21024]; + u8 _res15[0x45004 - 0x21024]; u32 gcc_apcs_clock_branch_en_vote; };
@@ -160,10 +179,10 @@ int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); -void clock_configure_spi(int blsp, uint32_t hz); +void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); -void clock_enable_spi(int blsp); -void clock_disable_spi(int blsp); +void clock_enable_spi(int blsp, int qup); +void clock_disable_spi(int blsp, int qup);
#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32240 )
Change subject: qcs405: clock: Update SPI API ......................................................................
Patch Set 1:
(18 comments)
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c:
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@218 PS1, Line 218: if (blsp == 1) that open brace { should be on the previous line
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@220 PS1, Line 220: switch (qup) { switch and case should be at the same indent
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@222 PS1, Line 222: spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup0_spi_clk; line over 80 characters
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@225 PS1, Line 225: spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup1_spi_clk; line over 80 characters
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@228 PS1, Line 228: spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup2_spi_clk; line over 80 characters
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@231 PS1, Line 231: spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup3_spi_clk; line over 80 characters
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@234 PS1, Line 234: spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk; line over 80 characters
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@236 PS1, Line 236: } code indent should use tabs where possible
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@236 PS1, Line 236: } please, no spaces at the start of a line
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@237 PS1, Line 237: } code indent should use tabs where possible
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@237 PS1, Line 237: } please, no spaces at the start of a line
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@238 PS1, Line 238: else if (blsp == 2) else should follow close brace '}'
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@259 PS1, Line 259: if (blsp == 1) that open brace { should be on the previous line
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@261 PS1, Line 261: switch (qup) { switch and case should be at the same indent
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@279 PS1, Line 279: else if (blsp == 2) else should follow close brace '}'
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@287 PS1, Line 287: if (blsp == 1) that open brace { should be on the previous line
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@289 PS1, Line 289: switch (qup) { switch and case should be at the same indent
https://review.coreboot.org/#/c/32240/1/src/soc/qualcomm/qcs405/clock.c@308 PS1, Line 308: else if (blsp == 2) else should follow close brace '}'
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32240 )
Change subject: qcs405: clock: Update SPI API ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32240
to look at the new patch set (#2).
Change subject: qcs405: clock: Update SPI API ......................................................................
qcs405: clock: Update SPI API
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405.
Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain shefjain@codeaurora.org Signed-off-by: Taniya Das tdas@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h 2 files changed, 109 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32240/2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32240 )
Change subject: qcs405: clock: Update SPI API ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32240 )
Change subject: qcs405: clock: Update SPI API ......................................................................
qcs405: clock: Update SPI API
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405.
Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain shefjain@codeaurora.org Signed-off-by: Taniya Das tdas@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h 2 files changed, 109 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 369bcdf..ebad13b 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -209,11 +209,38 @@ clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); }
-void clock_configure_spi(int blsp, uint32_t hz) +void clock_configure_spi(int blsp, int qup, uint32_t hz) { - struct qcs405_clock *spi_clk = (blsp == 1) ? - (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk - : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + struct qcs405_clock *spi_clk = 0; + + if (blsp == 1) { + switch (qup) { + case 0: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup0_spi_clk; + break; + case 1: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup1_spi_clk; + break; + case 2: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup2_spi_clk; + break; + case 3: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup3_spi_clk; + break; + case 4: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup4_spi_clk; + break; + } + } else if (blsp == 2) + spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } @@ -228,38 +255,66 @@ clock_disable(&gcc->blsp1_uart2_apps_cbcr); }
-void clock_enable_spi(int blsp) +void clock_enable_spi(int blsp, int qup) { - (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); }
-void clock_disable_spi(int blsp) +void clock_disable_spi(int blsp, int qup) { - (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + }
void clock_init(void) { - clock_configure_gpll0(); - - clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, - ARRAY_SIZE(uart_cfg)); - - clock_enable(&gcc->blsp1_uart2_apps_cbcr); clock_enable_vote(&gcc->blsp1_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP1_AHB_CLK_ENA);
- clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); - - clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); clock_enable_vote(&gcc->blsp2_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP2_AHB_CLK_ENA); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index d0f307b..8638128 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -21,7 +21,6 @@ #define BLSP2_AHB_CLK_ENA 20 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_800MHZ 1 -#define REG(addr) ((void *)addr)
/** * USB BCR registers @@ -66,28 +65,48 @@ u32 blsp1_bcr; u32 blsp1_sleep_cbcr; u32 blsp1_ahb_cbcr; - u8 _res1[0x3028 - 0x100c]; + struct qcs405_rcg gcc_blsp_uart_sim_rcg; + u8 _res1[0x2000 - 0x1014]; + u32 blsp1_qup1_bcr; + u32 blsp1_qup1_spi_apps_cbcr; + u8 _res2[0x2024 - 0x2008]; + struct qcs405_clock blsp1_qup1_spi_clk; + u8 _res3[0x3008-0x2038]; + u32 blsp1_qup2_bcr; + u32 blsp1_qup2_spi_apps_cbcr; + u8 _res4[0x3014 - 0x3010]; + struct qcs405_clock blsp1_qup2_spi_clk; u32 blsp1_uart2_bcr; u32 blsp1_uart2_apps_cbcr; u32 blsp1_uart2_sim_cbcr; struct qcs405_clock blsp1_uart2_apps_clk; - u8 _res2[0x5018 - 0x3048]; + u8 _res5[0x4018 - 0x3048]; + u32 blsp1_qup3_bcr; + u32 blsp1_qup3_spi_apps_cbcr; + u8 _res6[0x4024 - 0x4020]; + struct qcs405_clock blsp1_qup3_spi_clk; + u8 _res7[0x5018 - 0x4038]; u32 blsp1_qup4_bcr; u32 blsp1_qup4_spi_apps_cbcr; - u8 _res3[0x5024 - 0x5020]; + u8 _res8[0x5024 - 0x5020]; struct qcs405_clock blsp1_qup4_spi_clk; - u8 _res4[0xB000 - 0x5038]; + u8 _res9[0x6020 - 0x5038]; + u32 blsp1_qup0_bcr; + u32 blsp1_qup0_spi_apps_cbcr; + u8 _res10[0x6034 - 0x6028]; + struct qcs405_clock blsp1_qup0_spi_clk; + u8 _res11[0xB000 - 0x6048]; u32 blsp2_bcr; u32 blsp2_sleep_cbcr; u32 blsp2_ahb_cbcr; - u8 _res5[0xC000 - 0xB00C]; + u8 _res12[0xC000 - 0xB00C]; u32 blsp2_qup0_bcr; u32 blsp2_qup0_spi_apps_cbcr; - u8 _res6[0xC024 - 0xC008]; + u8 _res13[0xC024 - 0xC008]; struct qcs405_clock blsp2_qup0_spi_clk; - u8 _res7[0x21000 - 0xC038]; + u8 _res14[0x21000 - 0xC038]; struct qcs405_gpll gpll0; - u8 _res8[0x45004 - 0x21024]; + u8 _res15[0x45004 - 0x21024]; u32 gcc_apcs_clock_branch_en_vote; };
@@ -160,10 +179,10 @@ int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); -void clock_configure_spi(int blsp, uint32_t hz); +void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); -void clock_enable_spi(int blsp); -void clock_disable_spi(int blsp); +void clock_enable_spi(int blsp, int qup); +void clock_disable_spi(int blsp, int qup);
#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__
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