[M] Change in coreboot[main]: mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Yang Wu, Yu-Ping Wu.

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email )

Change subject: mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep
......................................................................

Patch Set 3:

(10 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/79064/comment/f866d9dc_064678be :
PS3, Line 7: mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep
mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650

https://review.coreboot.org/c/coreboot/+/79064/comment/4d9ef29f_434fa353 :
PS3, Line 9: Chinchou uses I2S1 and I2C5 to do the Devbeep in Depthcharge.
Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge.

https://review.coreboot.org/c/coreboot/+/79064/comment/61228522_f51db5af :
PS3, Line 10: 
BRANCH=corsola

https://review.coreboot.org/c/coreboot/+/79064/comment/e62484d2_bdad3643 :
PS3, Line 12: Verify Devbeep at Depthcharge console
Verify `devbeep` in depthcharge console

File src/mainboard/google/corsola/mainboard.c:

https://review.coreboot.org/c/coreboot/+/79064/comment/7fe00914_7380f4ef :
PS3, Line 29: configure_audio_ALC5645
what about configure_alc5645() ?

https://review.coreboot.org/c/coreboot/+/79064/comment/6b78bdde_fcac07c5 :
PS3, Line 39: Timing
timing

https://review.coreboot.org/c/coreboot/+/79064/comment/714f257a_e6df926b :
PS3, Line 39: i2c
I2C

https://review.coreboot.org/c/coreboot/+/79064/comment/b1d6234a_cccd1d39 :
PS3, Line 42: set
Set

File src/soc/mediatek/mt8186/include/soc/pll.h:

https://review.coreboot.org/c/coreboot/+/79064/comment/1cb83cd8_c5ed3e4c :
PS3, Line 11: #include <assert.h>
move it to pll.c

File src/soc/mediatek/mt8186/pll.c:

https://review.coreboot.org/c/coreboot/+/79064/comment/b80a369c_43607324 :
PS3, Line 591: void mt_pll_set_aud_div(u32 rate)
             : {
             : 	u32 mclk_div;
             : 	u32 apll_clock = APLL2_CK_HZ;
             : 	int apll1 = 0;
             : 
             : 	if (rate % 11025 == 0) {
             : 		/* use APLL1 instead */
             : 		apll1 = 1;
             : 		apll_clock = APLL1_CK_HZ;
             : 	}
             : 	/* I2S1 clock */
             : 	mclk_div = (apll_clock / 256 / rate) - 1;
             : 	assert(apll_clock == rate * 256 * (mclk_div + 1));
             : 
             : 	if (apll1) {
             : 		/* mclk */
             : 		clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
             : 		clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8,
             : 			     mclk_div << 8);
             : 		/* bclk */
             : 		clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24,
             : 			     7 << 24);
             : 	} else {
             : 		/* mclk */
             : 		setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
             : 		clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8,
             : 			     mclk_div << 8);
             : 		/* bclk */
             : 		clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28,
             : 			     7 << 28);
             : 	}
             : }
Leave this part for Jiaxin to review.