Change in coreboot[master]: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB ...
Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating error status registered (such as MCA MSRs) to list fatal errors happened during the previous boot session.
The header file supports 3 different error source types. CPX-SP FSP supports only McBankType.
Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Signed-off-by: Jonathan Zhang jonzhang@fb.com --- A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 1 file changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44973/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h new file mode 100644 index 0000000..9241692 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -0,0 +1,83 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _PREV_BOOT_ERR_SRC_GUID_H_ +#define _PREV_BOOT_ERR_SRC_GUID_H_ + +#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \ + 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \ + 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ + } + +#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 + +typedef struct { +UINT16 Length; // Actual size of the error sources used in the HOB +UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO +}PREV_BOOT_ERR_SRC_HOB; + +typedef struct{ +UINT8 Type; // McBankType = 1; +UINT8 Segment; +UINT8 Socket; +UINT16 ApicId; // ApicId is Needed only if it a core McBank. +UINT16 McBankNum; +UINT64 McBankStatus; +UINT64 McbankAddr; +UINT64 McBankMisc; +} MCBANK_ERR_INFO; + +typedef struct { +UINT8 Type; // PciExType =2 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT32 AerUncErrSts; +UINT8 AerHdrLogData[16]; +} PCI_EX_ERR_INFO; + +typedef struct { +UINT8 Type; // Other Csr error type =3 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT16 offset; +UINT32 Value; +} CSR_ERR_INFO; + +typedef enum { + McBankType = 1, + PciExType, + CsrOtherType +} ERROR_ACCESS_TYPE; + +#endif
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h:
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 2: BR Remove?
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 42: UINT16 Length; // Actual size of the error sources used in the HOB : UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO indent?
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 47: UINT8 Type; // McBankType = 1; : UINT8 Segment; : UINT8 Socket; : UINT16 ApicId; // ApicId is Needed only if it a core McBank. : UINT16 McBankNum; : UINT64 McBankStatus; : UINT64 McbankAddr; : UINT64 McBankMisc; indent?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2: Code-Review+1
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2:
(3 comments)
Thanks!
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h:
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 2: BR
Remove?
The code under vendorcode directory is from vendors as-is, so it does not subject to coreboot coding standard.
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 42: UINT16 Length; // Actual size of the error sources used in the HOB : UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO
indent?
This is copy & pasted from Intel as-is.
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 47: UINT8 Type; // McBankType = 1; : UINT8 Segment; : UINT8 Socket; : UINT16 ApicId; // ApicId is Needed only if it a core McBank. : UINT16 McBankNum; : UINT64 McBankStatus; : UINT64 McbankAddr; : UINT64 McBankMisc;
indent?
This is copy & pasted from Intel as-is.
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h:
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 2: BR
The code under vendorcode directory is from vendors as-is, so it does not subject to coreboot coding […]
Ack
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 42: UINT16 Length; // Actual size of the error sources used in the HOB : UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO
This is copy & pasted from Intel as-is.
Ack
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 47: UINT8 Type; // McBankType = 1; : UINT8 Segment; : UINT8 Socket; : UINT16 ApicId; // ApicId is Needed only if it a core McBank. : UINT16 McBankNum; : UINT64 McBankStatus; : UINT64 McbankAddr; : UINT64 McBankMisc;
This is copy & pasted from Intel as-is.
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h:
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 2: BR
Ack
Maybe someone should tell Intel about these cosmetic horrors? 😄
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h:
https://review.coreboot.org/c/coreboot/+/44973/2/src/vendorcode/intel/fsp/fs... PS2, Line 2: BR
Maybe someone should tell Intel about these cosmetic horrors? 😄
This is a doxygen marker. That being said, there are many cosmetic horrors.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ......................................................................
src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating error status registered (such as MCA MSRs) to list fatal errors happened during the previous boot session.
The header file supports 3 different error source types. CPX-SP FSP supports only McBankType.
Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Signed-off-by: Jonathan Zhang jonzhang@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973 Reviewed-by: Christian Walter christian.walter@9elements.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 1 file changed, 83 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h new file mode 100644 index 0000000..9241692 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -0,0 +1,83 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _PREV_BOOT_ERR_SRC_GUID_H_ +#define _PREV_BOOT_ERR_SRC_GUID_H_ + +#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \ + 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \ + 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ + } + +#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 + +typedef struct { +UINT16 Length; // Actual size of the error sources used in the HOB +UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO +}PREV_BOOT_ERR_SRC_HOB; + +typedef struct{ +UINT8 Type; // McBankType = 1; +UINT8 Segment; +UINT8 Socket; +UINT16 ApicId; // ApicId is Needed only if it a core McBank. +UINT16 McBankNum; +UINT64 McBankStatus; +UINT64 McbankAddr; +UINT64 McBankMisc; +} MCBANK_ERR_INFO; + +typedef struct { +UINT8 Type; // PciExType =2 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT32 AerUncErrSts; +UINT8 AerHdrLogData[16]; +} PCI_EX_ERR_INFO; + +typedef struct { +UINT8 Type; // Other Csr error type =3 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT16 offset; +UINT32 Value; +} CSR_ERR_INFO; + +typedef enum { + McBankType = 1, + PciExType, + CsrOtherType +} ERROR_ACCESS_TYPE; + +#endif
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Angel Pons (Code Review) -
Christian Walter (Code Review)
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Jonathan Zhang (Code Review)
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Patrick Georgi (Code Review)