Change in ...coreboot[master]: Doc/mb/asrock/h110m: update info about PEG

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31949

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 6 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/1

diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md
index 7bc38ff..c9be798 100644
--- a/Documentation/mainboard/asrock/h110m-dvs.md
+++ b/Documentation/mainboard/asrock/h110m-dvs.md
@@ -23,22 +23,10 @@

Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in
 the coreboot or download the latest version from [github][FSP github].
-
-You must use [Intel Binary Configuration Tool] BCT to set the following
-parameters in FSP.fd to initialize the PEG x16 port:
-
-```eval_rst
-  Peg0Enable = Enable
-  Peg0MaxLinkSpeed = Gen3
-  Peg0MaxLinkWidth = Auto
-```
-
-BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated
-into the coreboot image. If PEG port is not used, you can get these files
-without BTC:
+You must prepare the FSP for integration into the coreboot image:

```bash
-# split FSP.fd
+# split FSP.fd: Fsp_M.fd and Fsp_S.fd should be used in building the image
 python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd
 ```

@@ -97,10 +85,9 @@

## Known issues

-- The VGA port doesn't work.
-
-- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1).
-  It takes more time to research the schematic of this board.
+- The VGA port doesn't work. Discrete graphic card is used as primary
+  device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not
+  set). Dynamic switching between iGPU and PEG is not yet supported.

- SuperIO GPIO pin is used to reset Realtek chip. However, since the
   Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network
@@ -121,7 +108,7 @@

- integrated graphics init with libgfxinit (see [Known issues](#known-issues))
 - PCIe x1
-- PEG x16 Gen1 (see [Known issues](#known-issues))
+- PEG x16 Gen3
 - SATA
 - USB
 - serial port
@@ -131,7 +118,6 @@

## TODO

-- PEG x16 Gen3
 - NCT6791D GPIOs
 - onboard network (see [Known issues](#known-issues))
 - S3 suspend/resume
@@ -156,7 +142,6 @@

[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
 [FSP github]: https://github.com/IntelFsp/FSP
-[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT
 [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2...
 [flashrom]: https://flashrom.org/Flashrom
 [H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
PS3, Line 26: You must prepare the FSP for integration into the coreboot image:
as patching is no longer necessary, can all the preparation steps be removed?

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
PS3, Line 29: # split FSP.fd: Fsp_M.fd and Fsp_S.fd should be used in building the image
isn't it automatically split by the build process?

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31949

to look at the new patch set (#4).

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 6 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/4

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31949

to look at the new patch set (#5).

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 10 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/5

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
PS3, Line 26: You must prepare the FSP for integration into the coreboot image:
> as patching is no longer necessary, can all the preparation steps be removed?

I removed it

https://review.coreboot.org/#/c/31949/3/Documentation/mainboard/asrock/h110m... 
PS3, Line 29: # split FSP.fd: Fsp_M.fd and Fsp_S.fd should be used in building the image
> isn't it automatically split by the build process?

Yes, you are right. If I use CONFIG_FSP_USE_REPO, then the build system split fsp and adds it to the image. I removed it

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 5: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/31949/5/Documentation/mainboard/asrock/h110m... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/5/Documentation/mainboard/asrock/h110m... 
PS5, Line 8: Intel company provides [Firmware Support Package (2.0)](../../../Documentation/soc/intel/fsp/index.md)
           : (intel FSP 2.0) to initialize this generation silicon. Please see this
           : [document](../../../Documentation/soc/intel/code_development_model/code_development_model.md).
Fix the links in a separate commit?

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31949

to look at the new patch set (#6).

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 7 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/6

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/#/c/31949/5/Documentation/mainboard/asrock/h110m... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/5/Documentation/mainboard/asrock/h110m... 
PS5, Line 8: Intel company provides [Firmware Support Package (2.0)](../../../Documentation/soc/intel/fsp/index.md)
           : (intel FSP 2.0) to initialize this generation silicon. Please see this
           : [document](../../../Documentation/soc/intel/code_development_model/code_development_model.md).
> Fix the links in a separate commit?

Ok. Done 
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 17:

(1 comment)

https://review.coreboot.org/#/c/31949/17/Documentation/mainboard/asrock/h110... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/17/Documentation/mainboard/asrock/h110... 
PS17, Line 36: ./util/scripts/config --set-str CONFIG_FSP_M_FILE "$(obj)/Fsp_M.fd"
             : ./util/scripts/config --set-str CONFIG_FSP_S_FILE "$(obj)/Fsp_S.fd"
Aren't these set by default?

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31949

to look at the new patch set (#18).

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 5 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/18

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 18:

(1 comment)

https://review.coreboot.org/#/c/31949/17/Documentation/mainboard/asrock/h110... 
File Documentation/mainboard/asrock/h110m-dvs.md:

https://review.coreboot.org/#/c/31949/17/Documentation/mainboard/asrock/h110... 
PS17, Line 36: ./util/scripts/config --set-str CONFIG_FSP_M_FILE "$(obj)/Fsp_M.fd"
             : ./util/scripts/config --set-str CONFIG_FSP_S_FILE "$(obj)/Fsp_S.fd"
> Aren't these set by default?

removed

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31949

to look at the new patch set (#19).

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 5 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/19

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 19: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Patch Set 19: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31949 )

Change subject: Doc/mb/asrock/h110m: update info about PEG
......................................................................

Doc/mb/asrock/h110m: update info about PEG

- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949
Reviewed-by: Patrick Rudolph 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M Documentation/mainboard/asrock/h110m-dvs.md
1 file changed, 5 insertions(+), 31 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Patrick Rudolph: Looks good to me, approved

diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md
index 0227684..66d491d 100644
--- a/Documentation/mainboard/asrock/h110m-dvs.md
+++ b/Documentation/mainboard/asrock/h110m-dvs.md
@@ -21,27 +21,6 @@
 +-----------------------------+-------------------+-------------------+
 ```

-Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in
-the coreboot or download the latest version from [github][FSP github].
-
-You must use [Intel Binary Configuration Tool] BCT to set the following
-parameters in FSP.fd to initialize the PEG x16 port:
-
-```
-Peg0Enable = Enable
-Peg0MaxLinkSpeed = Gen3
-Peg0MaxLinkWidth = Auto
-```
-
-BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated
-into the coreboot image. If PEG port is not used, you can get these files
-without BTC:
-
-```bash
-# split FSP.fd
-python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd
-```
-
 ## Building coreboot

The following steps set the default parameters for this board to build a
@@ -53,8 +32,7 @@
 ./util/scripts/config --enable VENDOR_ASROCK
 ./util/scripts/config --enable BOARD_ASROCK_H110M_DVS
 ./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES
-./util/scripts/config --set-str CONFIG_FSP_M_FILE "/path/to/Fsp_M.fd"
-./util/scripts/config --set-str CONFIG_FSP_S_FILE "/path/to/Fsp_S.fd"
+./util/scripts/config --enable CONFIG_FSP_USE_REPO
 ./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx"
 make olddefconfig
 ```
@@ -97,10 +75,9 @@

## Known issues

-- The VGA port doesn't work.
-
-- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1).
-  It takes more time to research the schematic of this board.
+- The VGA port doesn't work. Discrete graphic card is used as primary
+  device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not
+  set). Dynamic switching between iGPU and PEG is not yet supported.

- SuperIO GPIO pin is used to reset Realtek chip. However, since the
   Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network
@@ -121,7 +98,7 @@

- integrated graphics init with libgfxinit (see [Known issues](#known-issues))
 - PCIe x1
-- PEG x16 Gen1 (see [Known issues](#known-issues))
+- PEG x16 Gen3
 - SATA
 - USB
 - serial port
@@ -131,7 +108,6 @@

## TODO

-- PEG x16 Gen3
 - NCT6791D GPIOs
 - onboard network (see [Known issues](#known-issues))
 - S3 suspend/resume
@@ -155,8 +131,6 @@
 ```

[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
-[FSP github]: https://github.com/IntelFsp/FSP
-[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT
 [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2...
 [flashrom]: https://flashrom.org/Flashrom
 [H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf