Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)

[Angel Pons (Code Review)]

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 )

Change subject: src/intel/xeon_sp: add hardware error support (HEST)
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Patch Set 18: -Code-Review

(2 comments)

File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:

https://review.coreboot.org/c/coreboot/+/52090/comment/057720ab_d5cdb1ba 
PS18, Line 27: ,	8, 	// 0x40 - 0x48 Hest log buffer
> runtime ASL code does not use it.  But runtime SMM uses GNVS to retrieve the hest log address.

Where in SMM is this being used? I can't see it.

File src/soc/intel/xeon_sp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/52090/comment/c9b403ed_1218951c 
PS18, Line 19: ifeq ($(CONFIG_SOC_INTEL_XEON_RAS),y)
             : subdirs-y += ras
             : endif
Much simpler:

subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras