Change in coreboot[master]: util/spd_tools/spd_gen: Add support for Sabrina SoC

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61542 )

Change subject: util/spd_tools/spd_gen: Add support for Sabrina SoC
......................................................................

util/spd_tools/spd_gen: Add support for Sabrina SoC

Add support to generate SPD binary for Sabrina SoC. Mainboards using
Sabrina SoC are planning to use LP5 memory technology. Some of the SPD
bytes expected by Sabrina differ from the existing ADL. To start with,
memory training code for Sabrina expects SPD Revision 1.1. More patches
will follow to accommodate additional differences.

BUG=b:211510456
TEST=make -C util/spd_tools.
Generate SPD binaries for the existing memory parts in
lp5/memory_parts.json and observe that SPDs for Sabrina is generated as
a separate set without impacting the ADL mainboards.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df
---
M util/spd_tools/src/spd_gen/lp5.go
M util/spd_tools/src/spd_gen/spd_gen.go
2 files changed, 33 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61542/1

diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go
index 2e52bd5..db8c829 100644
--- a/util/spd_tools/src/spd_gen/lp5.go
+++ b/util/spd_tools/src/spd_gen/lp5.go
@@ -55,6 +55,10 @@
    getVal   LP5SPDAttribFunc
 }

+type LP5Set struct {
+	SPDRevision    byte
+}
+
 /* ------------------------------------------------------------------------------------------ */
 /*                                         Constants                                          */
 /* ------------------------------------------------------------------------------------------ */
@@ -100,9 +104,13 @@
    LP5SPDValueSize = 0x23

/*
-	 * Revision 1.0.
+	 * Revision 1.0. Expected by ADL
     */
-	LP5SPDValueRevision = 0x10
+	LP5SPDValueRevision1_0 = 0x10
+	/*
+	 * Revision 1.1. Expected by Sabrina
+	 */
+	LP5SPDValueRevision1_1 = 0x11

/*
     * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13.
@@ -177,6 +185,16 @@

var LP5PlatformSetMap = map[int][]int{
    0: {PlatformADL},
+	1: {PlatformSBR},
+}
+
+var LP5SetInfo = map[int]LP5Set{
+	0: {
+		SPDRevision: LP5SPDValueRevision1_0,
+	},
+	1: {
+		SPDRevision: LP5SPDValueRevision1_1,
+	},
 }

var LP5PartAttributeMap = map[string]LP5MemAttributes{}
@@ -280,7 +298,7 @@

var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{
    LP5SPDIndexSize:               {constVal: LP5SPDValueSize},
-	LP5SPDIndexRevision:           {constVal: LP5SPDValueRevision},
+	LP5SPDIndexRevision:           {getVal: LP5EncodeSPDRevision},
    LP5SPDIndexMemoryType:         {constVal: LP5SPDValueMemoryType},
    LP5SPDIndexModuleType:         {constVal: LP5SPDValueModuleType},
    LP5SPDIndexDensityBanks:       {getVal: LP5EncodeDensityBanks},
@@ -309,6 +327,16 @@
 /* ------------------------------------------------------------------------------------------ */
 /*                                        Functions                                           */
 /* ------------------------------------------------------------------------------------------ */
+func LP5EncodeSPDRevision(memAttribs *LP5MemAttributes) byte {
+	f, ok := LP5SetInfo[LP5CurrSet]
+
+	if ok == false {
+		return 0
+	}
+
+	return f.SPDRevision
+
+}

func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte {
    var b byte
diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go
index 6cc9102..9e939f0 100644
--- a/util/spd_tools/src/spd_gen/spd_gen.go
+++ b/util/spd_tools/src/spd_gen/spd_gen.go
@@ -72,6 +72,7 @@
    PlatformJSL
    PlatformPCO
    PlatformCZN
+	PlatformSBR
    PlatformMax
 )

@@ -90,6 +91,7 @@
    PlatformJSL: "JSL",
    PlatformPCO: "PCO",
    PlatformCZN: "CZN",
+	PlatformSBR: "SBR",
 }

var memTechMap = map[string]memTech{