[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Disable DQS interleaving

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86268?usp=email )

Change subject: mb/starlabs/starbook/mtl: Disable DQS interleaving
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mb/starlabs/starbook/mtl: Disable DQS interleaving

This causes FSP-M to fail memory training, so disable it.

Change-Id: I4a3544a153d6d4da95c4d679665d9c92bd04ed87
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86268
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/starlabs/starbook/variants/mtl/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 956f9c5..14b2664 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -11,6 +11,9 @@
    	.type = MEM_TYPE_DDR5,
    	.ect = false,
    	.UserBd = BOARD_TYPE_MOBILE,
+		.ddr_config = {
+			.dq_pins_interleaved = false,
+		}
    };

const bool half_populated = false;