Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related variables

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related variables
......................................................................

soc/intel/elkhartlake: Update SA & PM related variables

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/1

diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h
index 5ba40bc..0246673 100644
--- a/src/soc/intel/elkhartlake/include/soc/iomap.h
+++ b/src/soc/intel/elkhartlake/include/soc/iomap.h
@@ -47,8 +47,8 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000

-#define MCH_BASE_ADDRESS	0xfea80000
-#define MCH_BASE_SIZE		0x8000
+#define MCH_BASE_ADDRESS	0xfec80000
+#define MCH_BASE_SIZE		0x80000

#define EARLY_GSPI_BASE_ADDRESS	0xfe011000

diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h
index 11d6663..6ebbbfa 100644
--- a/src/soc/intel/elkhartlake/include/soc/pm.h
+++ b/src/soc/intel/elkhartlake/include/soc/pm.h
@@ -65,7 +65,7 @@
 #define  SMI_ON_SLP_EN_STS_BIT		4
 #define  LEGACY_USB_STS_BIT		3
 #define  BIOS_STS_BIT			2
-#define GPE_CNTL		0x42
+#define GPE_CNTL		0x40
 #define  SWGPE_CTRL		(1 << 1)
 #define DEVACT_STS		0x44
 #define PM2_CNT			0x50

[Lean Sheng Tan (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45077

to look at the new patch set (#2).

Change subject: soc/intel/elkhartlake: Update SA & PM related variables
......................................................................

soc/intel/elkhartlake: Update SA & PM related variables

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/2

[Lean Sheng Tan (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45077

to look at the new patch set (#3).

Change subject: soc/intel/elkhartlake: Update SA & PM related variables
......................................................................

soc/intel/elkhartlake: Update SA & PM related variables

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/3

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related variables
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/45077/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45077/3//COMMIT_MSG@7 
PS3, Line 7: variables
defines?

Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related definitions

[Lean Sheng Tan (Code Review)]

Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Aamir Bohra, Werner Zeh, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45077

to look at the new patch set (#4).

Change subject: soc/intel/elkhartlake: Update SA & PM related definitions
......................................................................

soc/intel/elkhartlake: Update SA & PM related definitions

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/4

Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related definitions

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related definitions
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45077/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45077/3//COMMIT_MSG@7 
PS3, Line 7: variables
> defines?

Done

Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related definitions

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related definitions
......................................................................

soc/intel/elkhartlake: Update SA & PM related definitions

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h
index 5ba40bc..0246673 100644
--- a/src/soc/intel/elkhartlake/include/soc/iomap.h
+++ b/src/soc/intel/elkhartlake/include/soc/iomap.h
@@ -47,8 +47,8 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000

-#define MCH_BASE_ADDRESS	0xfea80000
-#define MCH_BASE_SIZE		0x8000
+#define MCH_BASE_ADDRESS	0xfec80000
+#define MCH_BASE_SIZE		0x80000

#define EARLY_GSPI_BASE_ADDRESS	0xfe011000

diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h
index 11d6663..6ebbbfa 100644
--- a/src/soc/intel/elkhartlake/include/soc/pm.h
+++ b/src/soc/intel/elkhartlake/include/soc/pm.h
@@ -65,7 +65,7 @@
 #define  SMI_ON_SLP_EN_STS_BIT		4
 #define  LEGACY_USB_STS_BIT		3
 #define  BIOS_STS_BIT			2
-#define GPE_CNTL		0x42
+#define GPE_CNTL		0x40
 #define  SWGPE_CTRL		(1 << 1)
 #define DEVACT_STS		0x44
 #define PM2_CNT			0x50

Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related definitions

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related definitions
......................................................................

Patch Set 5:

Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8
"QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18165
"QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18164
"QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/18163
"QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18162
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/18161
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/18168
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18167
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18166

Please note: This test is under development and might not be accurate at all!