the following patch was just integrated into master: commit c97e042a9bda9994409869369e1cbda551dc65cf Author: Matt DeVillier matt.devillier@gmail.com Date: Thu Feb 16 11:36:16 2017 -0600
lynxpoint/broadwell: fix PCH power optimizer
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC Configuration; offset 0x33c8) causes pre-OS display init to fail on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP driver is run after the register is set. A re-examination of Intel's reference code reveals that bit 7 should be set for the LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu, observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/18385 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth martinroth@google.com Reviewed-by: Duncan Laurie dlaurie@chromium.org
See https://review.coreboot.org/18385 for details.
-gerrit