[S] Change in coreboot[master]: device & commonlib: Update pci_scan_bus postcodes

[Martin L Roth (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/69201

to look at the new patch set (#2).

Change subject: device & commonlib: Update pci_scan_bus postcodes
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device & commonlib: Update pci_scan_bus postcodes

The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end

I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function.  I don't think all three are needed.

0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code.  Those postcodes should be adjusted to avoid conflicting.

Signed-off-by: Martin Roth 
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/device/pci_device.c
2 files changed, 37 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69201/2