Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Julien Viard de Galbert (Code Review)]

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Steve Mooney, Paul Menzel, Vanessa Eusebio, Patrick Rudolph, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/25442

to look at the new patch set (#22).

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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soc/intel/denverton_ns: Implement PCIe post config + lock

- Configure PCIe maximum payload size to fix Intel SSD
- Lock Down PCIe Configuration

Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert 
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M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/22