New patch to review for coreboot: COMe-bIP2: Initial take at getting the board to compile
Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14401
-gerrit
commit 6e0e5a91d1e5fce89eb0085b7a64a13ff94ca757 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Mon Mar 21 22:53:14 2016 -0700
COMe-bIP2: Initial take at getting the board to compile
Change-Id: Ib66dd38993b70b3114ae52a1a186f28122994e43 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/mainboard/kontron/come-bip2/Kconfig | 22 ++--- src/mainboard/kontron/come-bip2/Kconfig.name | 4 +- src/mainboard/kontron/come-bip2/Makefile.inc | 23 ----- src/mainboard/kontron/come-bip2/acpi/ec.asl | 9 +- src/mainboard/kontron/come-bip2/acpi/mainboard.asl | 62 ------------ src/mainboard/kontron/come-bip2/acpi/platform.asl | 14 --- src/mainboard/kontron/come-bip2/acpi/superio.asl | 17 ++-- src/mainboard/kontron/come-bip2/acpi/thermal.asl | 31 +----- src/mainboard/kontron/come-bip2/acpi_tables.c | 6 -- src/mainboard/kontron/come-bip2/chromeos.c | 109 --------------------- src/mainboard/kontron/come-bip2/chromeos.fmd | 38 ------- src/mainboard/kontron/come-bip2/dsdt.asl | 3 - src/mainboard/kontron/come-bip2/ec.c | 47 --------- src/mainboard/kontron/come-bip2/ec.h | 58 ----------- .../kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/mainboard.c | 56 ++--------- src/mainboard/kontron/come-bip2/mainboard_smi.c | 70 ------------- .../come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/onboard.h | 32 ------ src/mainboard/kontron/come-bip2/romstage.c | 43 ++------ .../come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/thermal.h | 4 +- 22 files changed, 35 insertions(+), 709 deletions(-)
diff --git a/src/mainboard/kontron/come-bip2/Kconfig b/src/mainboard/kontron/come-bip2/Kconfig index e61bba0..bd77158 100644 --- a/src/mainboard/kontron/come-bip2/Kconfig +++ b/src/mainboard/kontron/come-bip2/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GOOGLE_LINK +if BOARD_KONTRON_COME_BIP2
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -7,30 +7,24 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 - select EC_GOOGLE_CHROMEEC + select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT
-config CHROMEOS - select CHROMEOS_VBNV_CMOS - select LID_SWITCH - config MAINBOARD_DIR string - default google/link + default kontron/come-bip2
config MAINBOARD_PART_NUMBER string - default "Link" + default "COMe-bIP2"
config MMCONF_BASE_ADDRESS hex - default 0xf8000000 + default 0xf0000000
config MAX_CPUS int @@ -40,8 +34,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom"
-config GBB_HWID - string - depends on CHROMEOS - default "X86 LINK TEST 6638" -endif # BOARD_GOOGLE_LINK +endif # BOARD_KONTRON_COME_BIP2 diff --git a/src/mainboard/kontron/come-bip2/Kconfig.name b/src/mainboard/kontron/come-bip2/Kconfig.name index 289164b..5d4917b 100644 --- a/src/mainboard/kontron/come-bip2/Kconfig.name +++ b/src/mainboard/kontron/come-bip2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GOOGLE_LINK - bool "Link" +config BOARD_KONTRON_COME_BIP2 + bool "COMe-bIP2" diff --git a/src/mainboard/kontron/come-bip2/Makefile.inc b/src/mainboard/kontron/come-bip2/Makefile.inc index b79e4d3..5aaf562 100644 --- a/src/mainboard/kontron/come-bip2/Makefile.inc +++ b/src/mainboard/kontron/come-bip2/Makefile.inc @@ -13,33 +13,10 @@ ## GNU General Public License for more details. ##
-ramstage-y += ec.c - -romstage-y += chromeos.c -ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = elpida_4Gb_1600_x16 -SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 -SPD_SOURCES += micron_4Gb_1600_1.35v_x16 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '%o' 0x$$c); \ - done; \ - done > $@
-cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd romstage-y += gpio.c diff --git a/src/mainboard/kontron/come-bip2/acpi/ec.asl b/src/mainboard/kontron/come-bip2/acpi/ec.asl index 2e898ed..b5b8e2b 100644 --- a/src/mainboard/kontron/come-bip2/acpi/ec.asl +++ b/src/mainboard/kontron/come-bip2/acpi/ec.asl @@ -13,11 +13,4 @@ * GNU General Public License for more details. */
-/* mainboard configuration */ -#include "../ec.h" - -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> +/* NONE */ diff --git a/src/mainboard/kontron/come-bip2/acpi/mainboard.asl b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl index 01e99fa..817c2a8 100644 --- a/src/mainboard/kontron/come-bip2/acpi/mainboard.asl +++ b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl @@ -14,71 +14,9 @@ * GNU General Public License for more details. */
-#include <mainboard/google/link/onboard.h> - Scope (_SB) { - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - - // EC_LID_OUT is GPIO15 - Name(_PRW, Package(){0x1f, 0x05}) - } - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) } - - Device (TPAD) - { - Name (_ADR, 0x0) - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) - - // Trackpad Wake is GPIO12 - Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) - - Name(_CRS, ResourceTemplate() - { - // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - - // SMBUS Address 0x4b - VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } - }) - } - - Device (TSCR) - { - Name (_ADR, 0x0) - Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) - - // Touchscreen Wake is GPIO14 - Name(_PRW, Package(){0x1e, 0x03}) - - Name(_CRS, ResourceTemplate() - { - // PIRQG -> GSI22 - Interrupt (ResourceConsumer, Edge, ActiveLow) {22} - - // SMBUS Address 0x4a - VendorShort (ADDR) {0x4a} - }) - } } diff --git a/src/mainboard/kontron/come-bip2/acpi/platform.asl b/src/mainboard/kontron/come-bip2/acpi/platform.asl index c84736a..3639db7 100644 --- a/src/mainboard/kontron/come-bip2/acpi/platform.asl +++ b/src/mainboard/kontron/come-bip2/acpi/platform.asl @@ -27,19 +27,5 @@ Method(_PTS,1)
Method(_WAK,1) { - /* Update AC status */ - Store (_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) - Notify (_SB.PCI0.LPCB.EC0.AC, 0x80) - } - - /* Update LID status */ - Store (_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) - Notify (_SB.LID0, 0x80) - } - Return(Package(){0,0}) } diff --git a/src/mainboard/kontron/come-bip2/acpi/superio.asl b/src/mainboard/kontron/come-bip2/acpi/superio.asl index 266a67c..c3ad655 100644 --- a/src/mainboard/kontron/come-bip2/acpi/superio.asl +++ b/src/mainboard/kontron/come-bip2/acpi/superio.asl @@ -13,13 +13,12 @@ * GNU General Public License for more details. */
-/* mainboard configuration */ -#include "../ec.h" +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define W83627DHG_SHOW_UARTA // UARTA will be exposed +#define W83627DHG_SHOW_UARTB +#define W83627DHG_SHOW_KBC // +#define W83627DHG_SHOW_PS2M
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include "../../../../ec/google/chromeec/acpi/superio.asl" +/* ACPI code for SuperIO functions */ +#include <superio/winbond/w83627dhg/acpi/superio.asl> diff --git a/src/mainboard/kontron/come-bip2/acpi/thermal.asl b/src/mainboard/kontron/come-bip2/acpi/thermal.asl index 9163493..8c084bf 100644 --- a/src/mainboard/kontron/come-bip2/acpi/thermal.asl +++ b/src/mainboard/kontron/come-bip2/acpi/thermal.asl @@ -14,7 +14,7 @@ */
// Thermal Zone - +#if 0 Scope (_TZ) { ThermalZone (CRIT) @@ -41,34 +41,8 @@ Scope (_TZ)
Method (_TMP, 0, Serialized) { - // Get CPU Temperature from TIN9/PECI via EC - Store (_SB.PCI0.LPCB.EC0.TIN9, Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + // TODO: Get CPU Temperature from TIN9/PECI via SuperIO
- // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) Return (Local0) } } @@ -217,3 +191,4 @@ Scope (_TZ) } } } +#endif diff --git a/src/mainboard/kontron/come-bip2/acpi_tables.c b/src/mainboard/kontron/come-bip2/acpi_tables.c index a7f2c50..16e9be9 100644 --- a/src/mainboard/kontron/come-bip2/acpi_tables.c +++ b/src/mainboard/kontron/come-bip2/acpi_tables.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -60,11 +59,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0;
-#if CONFIG_CHROMEOS - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - acpi_update_thermal_table(gnvs);
// the lid is open by default. diff --git a/src/mainboard/kontron/come-bip2/chromeos.c b/src/mainboard/kontron/come-bip2/chromeos.c deleted file mode 100644 index d07e851..0000000 --- a/src/mainboard/kontron/come-bip2/chromeos.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> -#include "ec.h" -#include <ec/google/chromeec/ec.h> - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -#define GPIO_COUNT 6 - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - gpios->gpios[0].port = 57; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - /* Recovery: the "switch" comes from the EC */ - gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_lid_switch(); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button: hard-coded as not pressed; we'll detect later presses - * via SMI. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Developer: a tricky case on Link, there is no switch */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); -} -#endif - -int get_write_protect_state(void) -{ - return get_gpio(57); -} - -int get_lid_switch(void) -{ - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - - return !!(ec_switches & EC_SWITCH_LID_OPEN); -} - -/* The dev-switch is virtual on Link (and so handled elsewhere). */ -int get_developer_mode_switch(void) -{ - return 0; -} - -/* There are actually two recovery switches. One is the magic keyboard chord, - * the other is driven by Servo. */ -int get_recovery_mode_switch(void) -{ - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - u32 ec_events; - - /* If a switch is set, we don't need to look at events. */ - if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) - return 1; - - /* Else check if the EC has posted the keyboard recovery event. */ - ec_events = google_chromeec_get_events_b(); - - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} diff --git a/src/mainboard/kontron/come-bip2/chromeos.fmd b/src/mainboard/kontron/come-bip2/chromeos.fmd deleted file mode 100644 index 21b39c0..0000000 --- a/src/mainboard/kontron/come-bip2/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/kontron/come-bip2/dsdt.asl b/src/mainboard/kontron/come-bip2/dsdt.asl index be6a412..5aad74c 100644 --- a/src/mainboard/kontron/come-bip2/dsdt.asl +++ b/src/mainboard/kontron/come-bip2/dsdt.asl @@ -50,9 +50,6 @@ DefinitionBlock( } }
- #include "acpi/chromeos.asl" - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/kontron/come-bip2/ec.c b/src/mainboard/kontron/come-bip2/ec.c deleted file mode 100644 index acf1185..0000000 --- a/src/mainboard/kontron/come-bip2/ec.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void link_ec_init(void) -{ - printk(BIOS_DEBUG, "link_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S5_WAKE_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/kontron/come-bip2/ec.h b/src/mainboard/kontron/come-bip2/ec.h deleted file mode 100644 index af06772..0000000 --- a/src/mainboard/kontron/come-bip2/ec.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_EC_H -#define LINK_EC_H - -#include <ec/google/chromeec/ec_commands.h> - -#define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */ -#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ - -#define LINK_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define LINK_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define LINK_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define LINK_EC_S3_WAKE_EVENTS \ - (LINK_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define LINK_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#ifndef __ACPI__ -extern void link_ec_init(void); -#endif - -#endif // LINK_EC_H diff --git a/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex deleted file mode 100644 index ef36c39..0000000 --- a/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 10 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 81 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 42 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 02 fe 00 -11 52 00 00 00 07 7f 37 -45 42 4a 32 30 55 47 36 -45 42 55 30 2d 47 4e 2d -46 20 30 20 02 fe 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/mainboard.c b/src/mainboard/kontron/come-bip2/mainboard.c index 922061f..e1e4a7c 100644 --- a/src/mainboard/kontron/come-bip2/mainboard.c +++ b/src/mainboard/kontron/come-bip2/mainboard.c @@ -29,27 +29,10 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include "onboard.h" -#include "ec.h" #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <smbios.h> #include <device/pci.h> -#include <ec/google/chromeec/ec.h> - -/* placeholder for evenual link post. Not sure what we'll - * do but it will look nice - */ -void mainboard_post(u8 value) -{ - /* - * What you DO NOT want to do: push every post to the EC backlight. - * it seems cute but in practice it looks like a hardware failure. - * I'm leaving this here so we don't make this mistake again later. - * And it seems to break the SMP startup. - * google_chromeec_post(value); - */ -}
#if CONFIG_VGA_ROM_RUN static int int15_handler(void) @@ -142,25 +125,16 @@ static int int15_handler(void)
static void mainboard_init(device_t dev) { - /* Initialize the Embedded Controller */ - link_ec_init(); - - if (google_chromeec_get_board_version() == 0) { - /* If running on proto1 - enable reversion of gpio11. */ - u32 gpio_inv; - u16 gpio_base = pci_read_config16 - (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & - 0xfffc; - u16 gpio_inv_addr = gpio_base + GPI_INV; - gpio_inv = inl(gpio_inv_addr); - outl(gpio_inv | (1 << 11), gpio_inv_addr); - } + /* TBD */ }
-static int link_onboard_smbios_data(device_t dev, int *handle, +static int onboard_smbios_data(device_t dev, int *handle, unsigned long *current) { int len = 0; +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 0
len += smbios_write_type41( current, handle, @@ -171,24 +145,6 @@ static int link_onboard_smbios_data(device_t dev, int *handle, 0, /* device */ 0); /* function */
- len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - 0, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - 0, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - return len; }
@@ -198,7 +154,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = link_onboard_smbios_data; + dev->ops->get_smbios_data = onboard_smbios_data; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/kontron/come-bip2/mainboard_smi.c b/src/mainboard/kontron/come-bip2/mainboard_smi.c index d281742..c4221ab 100644 --- a/src/mainboard/kontron/come-bip2/mainboard_smi.c +++ b/src/mainboard/kontron/come-bip2/mainboard_smi.c @@ -23,74 +23,12 @@ #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h>
-/* Include EC functions */ -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } }
void mainboard_smi_sleep(u8 slp_typ) { - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - case 5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS); }
#define APMC_ACPI_EN 0xe1 @@ -100,16 +38,8 @@ int mainboard_smi_apmc(u8 apmc) { switch (apmc) { case APMC_ACPI_EN: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); break; case APMC_ACPI_DIS: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex deleted file mode 100644 index 7ed2663..0000000 --- a/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 ad 75 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/kontron/come-bip2/onboard.h b/src/mainboard/kontron/come-bip2/onboard.h deleted file mode 100644 index 7bc213b..0000000 --- a/src/mainboard/kontron/come-bip2/onboard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_ONBOARD_H -#define LINK_ONBOARD_H - -#define BOARD_LIGHTSENSOR_NAME "lightsensor" -#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 -#define BOARD_LIGHTSENSOR_IRQ 0 - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_I2C_ADDR 0x4b -#define BOARD_TRACKPAD_IRQ 20 -#define BOARD_TRACKPAD_WAKE_GPIO 0x1c - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a -#define BOARD_TOUCHSCREEN_IRQ 22 - -#endif diff --git a/src/mainboard/kontron/come-bip2/romstage.c b/src/mainboard/kontron/come-bip2/romstage.c index 8142845..fcdeb3c 100644 --- a/src/mainboard/kontron/come-bip2/romstage.c +++ b/src/mainboard/kontron/come-bip2/romstage.c @@ -31,7 +31,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> -#include "ec/google/chromeec/ec.h" +#include <superio/winbond/w83627dhg/w83627dhg.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> @@ -115,28 +115,10 @@ void rcba_config(void) RCBA32(FD) = reg32; }
-static uint8_t *locate_spd(void) +void mainboard_get_spd(spd_raw_data *spd) { - const int gpio_vector[] = {41, 42, 43, 10, -1}; - uint8_t *spd_file; - size_t spd_file_len; - int spd_index = get_gpios(gpio_vector); - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * 256)) { - printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); }
void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -157,9 +139,10 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 1, + .ec_present = 0, + .ddr3lv_support = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel @@ -187,8 +170,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - memcpy(pei_data->spd_data[0], locate_spd(), - sizeof(pei_data->spd_data[0])); }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -209,18 +190,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P13: Empty */ };
-void mainboard_get_spd(spd_raw_data *spd) { - memcpy(&spd[0], locate_spd(), 128); -} - void mainboard_early_init(int s3resume) { - if (!s3resume) { - /* This is the fastest way to let users know - * the Intel CPU is now alive. - */ - google_chromeec_kbbacklight(100); - } }
int mainboard_should_reset_usb(int s3resume) diff --git a/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex deleted file mode 100644 index 5beb5fc..0000000 --- a/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -f0 0a 3c 3c 01 40 83 01 -00 80 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ce 01 -00 00 00 00 00 00 6a 04 -4d 34 37 31 42 35 36 37 -34 42 48 30 2d 59 4b 30 -20 20 00 00 80 ce 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/thermal.h b/src/mainboard/kontron/come-bip2/thermal.h index 4a1f31b..af71849 100644 --- a/src/mainboard/kontron/come-bip2/thermal.h +++ b/src/mainboard/kontron/come-bip2/thermal.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */
-#ifndef LINK_THERMAL_H -#define LINK_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H
/* Config TDP Sensor ID */ #define CTDP_SENSOR_ID 9 /* PECI */
-
Stefan Reinauer