Change in coreboot[master]: soc/intel/{APL, GLK}: Use Intel SRAM common code.

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/22608

Change subject: soc/intel/{APL,GLK}: Use Intel SRAM common code.
......................................................................

soc/intel/{APL,GLK}: Use Intel SRAM common code.

Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa
Signed-off-by: V Sowmya 
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
D src/soc/intel/apollolake/sram.c
3 files changed, 1 insertion(+), 74 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22608/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index f568799..b21354e 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -88,6 +88,7 @@
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SPI
    select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
+	select SOC_INTEL_COMMON_BLOCK_SRAM
    select UDELAY_TSC
    select TSC_CONSTANT_RATE
    select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 14932dd..5fc07ae 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -62,7 +62,6 @@
 ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
-ramstage-y += sram.c
 ramstage-y += xdci.c
 ramstage-y += sd.c

diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c
deleted file mode 100644
index 70e1330..0000000
--- a/src/soc/intel/apollolake/sram.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <soc/pci_devs.h>
-#include <soc/iomap.h>
-
-static void read_resources(device_t dev)
-{
-	struct resource *res;
-	pci_dev_read_resources(dev);
-
-	res = new_resource(dev, PCI_BASE_ADDRESS_0);
-	res->base = SRAM_BASE_0;
-	res->size = SRAM_SIZE_0;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, PCI_BASE_ADDRESS_2);
-	res->base = SRAM_BASE_2;
-	res->size = SRAM_SIZE_2;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void set_resources(device_t dev)
-{
-	struct resource *res;
-	pci_dev_set_resources(dev);
-
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	pci_write_config32(dev, res->index, res->base);
-	dev->command |= PCI_COMMAND_MEMORY;
-	res->flags |= IORESOURCE_STORED;
-	report_resource_stored(dev, res, " SRAM BAR 0");
-
-	res = find_resource(dev, PCI_BASE_ADDRESS_2);
-	pci_write_config32(dev, res->index, res->base);
-	dev->command |= PCI_COMMAND_MEMORY;
-	res->flags |= IORESOURCE_STORED;
-	report_resource_stored(dev, res, " SRAM BAR 2");
-}
-
-static const struct device_operations device_ops = {
-	.read_resources		= read_resources,
-	.set_resources		= set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-};
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_APL_SRAM,
-	PCI_DEVICE_ID_INTEL_GLK_SRAM,
-	0,
-};
-
-static const struct pci_driver pmc __pci_driver = {
-	.ops	= &device_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.devices= pci_device_ids,
-};