Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )

Change subject: soc/intel/braswell: Add support for FSP MR2
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Patch Set 5:

(1 comment)
> IIRC, the original problem was that the current coreboot

source is incompatible with the upstream headers

correct, MR2 lacks quite a few UPDs used by Google

https://review.coreboot.org/#/c/29661/5/src/vendorcode/intel/fsp/fsp1_1/bras... 
File src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h:

https://review.coreboot.org/#/c/29661/5/src/vendorcode/intel/fsp/fsp1_1/bras... 
PS5, Line 566: /** Offset 0x02FE
this change is unguarded - is the currently listed offset incorrect for both MR2 and Google FSP?