HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41671 )
Change subject: src: Remove unused 'include <bootstate.h>' ......................................................................
src: Remove unused 'include <bootstate.h>'
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/tables.c M src/drivers/intel/fsp1_1/hob.c M src/ec/google/chromeec/ec.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/protectli/vault_kbl/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/picasso/chip.c M src/soc/intel/apollolake/elog.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/vbt.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/pmc.c M src/southbridge/intel/lynxpoint/smi.c 23 files changed, 0 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41671/1
diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index cde95f1..de56291 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/name.h> diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 3b1b76d..492674c 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <bootmem.h> -#include <bootstate.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d13939c..9a09cfd 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hlt.h> -#include <bootstate.h> #include <console/console.h> #include <fsp/util.h> #include <ip_checksum.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 6465960..89f137c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index c24479d..bc3bfc9 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> -#include <bootstate.h> #include <symbols.h>
void cbmem_run_init_hooks(int is_recovery) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index afc0618..2fb1e9e 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <imd.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 2f065ff..c95753f 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -2,7 +2,6 @@
#include <assert.h> #include <boot/coreboot_tables.h> -#include <bootstate.h> #include <bootmem.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6e0315b..6fde602 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <bootstate.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 287623e..dd40848 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 266094a4..962702f 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <bootstate.h> #include <soc/ramstage.h>
#include "gpio.h" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 8c9daf7..5de606d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <soc/ramstage.h> #include <variant/gpio.h>
diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 703af9d..5096dd3 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -4,7 +4,6 @@ #include <cbfs.h> #include <region_file.h> #include <timer.h> -#include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> #include <soc/iomap.h> diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index cf9b532..59e6255 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,7 +2,6 @@
#include <device/mmio.h> #include <timer.h> -#include <bootstate.h> #include <amdblocks/psp.h> #include <soc/iomap.h> #include "psp_def.h" diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 024e952..b103b3e 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -5,7 +5,6 @@ #include <cpu/amd/msr.h> #include <cbfs.h> #include <region_file.h> -#include <bootstate.h> #include <rules.h> #include <console/console.h> #include <amdblocks/psp.h> diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..9c26f35 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cpu/amd/mtrr.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 30d7b20..408017f 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <elog.h> diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 101ab92..893a6b6 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,6 @@
#include <arch/cpu.h> #include <acpi/acpi.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 2696777..93fcee2 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 3d0ba1a..690fb5f 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,7 +2,6 @@
#include <acpi/acpi.h> #include <bootmode.h> -#include <bootstate.h>
#include "vbt.h" #include <drivers/intel/gma/opregion.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a1ef06e..6ef01d8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <fsp/api.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 845becc..bfa59fe 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h> -#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 62e3711..bf3c77b 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -6,7 +6,6 @@ * Chapter number: 4 */
-#include <bootstate.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d57554..cddada1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h>
Hello build bot (Jenkins), Michał Żygowski, Lee Leahy, Huang Jin, Andrey Petrov, Patrick Rudolph, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41671
to look at the new patch set (#4).
Change subject: src: Remove unused 'include <bootstate.h>' ......................................................................
src: Remove unused 'include <bootstate.h>'
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/tables.c M src/drivers/intel/fsp1_1/hob.c M src/ec/google/chromeec/ec.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/protectli/vault_kbl/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/picasso/chip.c M src/soc/intel/apollolake/elog.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/vbt.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/pmc.c M src/southbridge/intel/lynxpoint/smi.c 23 files changed, 0 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41671/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41671 )
Change subject: src: Remove unused 'include <bootstate.h>' ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41671 )
Change subject: src: Remove unused 'include <bootstate.h>' ......................................................................
src: Remove unused 'include <bootstate.h>'
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/tables.c M src/drivers/intel/fsp1_1/hob.c M src/ec/google/chromeec/ec.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/protectli/vault_kbl/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/picasso/chip.c M src/soc/intel/apollolake/elog.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/vbt.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/pmc.c M src/southbridge/intel/lynxpoint/smi.c 23 files changed, 0 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index cde95f1..de56291 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/name.h> diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 3b1b76d..492674c 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <bootmem.h> -#include <bootstate.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d13939c..9a09cfd 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hlt.h> -#include <bootstate.h> #include <console/console.h> #include <fsp/util.h> #include <ip_checksum.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 233f61b..a97dfb3 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index c24479d..bc3bfc9 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> -#include <bootstate.h> #include <symbols.h>
void cbmem_run_init_hooks(int is_recovery) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index afc0618..2fb1e9e 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <imd.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d06a9e9..cb66c3b 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -2,7 +2,6 @@
#include <assert.h> #include <boot/coreboot_tables.h> -#include <bootstate.h> #include <bootmem.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6e0315b..6fde602 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <bootstate.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 287623e..dd40848 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 266094a4..962702f 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <bootstate.h> #include <soc/ramstage.h>
#include "gpio.h" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 8c9daf7..5de606d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <soc/ramstage.h> #include <variant/gpio.h>
diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 703af9d..5096dd3 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -4,7 +4,6 @@ #include <cbfs.h> #include <region_file.h> #include <timer.h> -#include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> #include <soc/iomap.h> diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index cf9b532..59e6255 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,7 +2,6 @@
#include <device/mmio.h> #include <timer.h> -#include <bootstate.h> #include <amdblocks/psp.h> #include <soc/iomap.h> #include "psp_def.h" diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 024e952..b103b3e 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -5,7 +5,6 @@ #include <cpu/amd/msr.h> #include <cbfs.h> #include <region_file.h> -#include <bootstate.h> #include <rules.h> #include <console/console.h> #include <amdblocks/psp.h> diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..9c26f35 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cpu/amd/mtrr.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 30d7b20..408017f 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <elog.h> diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 101ab92..893a6b6 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,6 @@
#include <arch/cpu.h> #include <acpi/acpi.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 2696777..93fcee2 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 3d0ba1a..690fb5f 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,7 +2,6 @@
#include <acpi/acpi.h> #include <bootmode.h> -#include <bootstate.h>
#include "vbt.h" #include <drivers/intel/gma/opregion.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a1ef06e..6ef01d8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <cbmem.h> #include <fsp/api.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 845becc..bfa59fe 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h> -#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 84a18e3..4d89870 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -7,7 +7,6 @@ */
#include <acpi/acpigen.h> -#include <bootstate.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d57554..cddada1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h>
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41671 )
Change subject: src: Remove unused 'include <bootstate.h>' ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4584 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4583 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4582 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4581
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)