Change in coreboot[master]: soc/amd/common: Add some ESPI register definitions

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51747 )

Change subject: soc/amd/common: Add some ESPI register definitions
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soc/amd/common: Add some ESPI register definitions

Use definitions instead of magic numbers
clean up some whitespace while I'm here.

BUG=b:183207262
TEST=Build

Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af
Signed-off-by: Martin Roth 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/include/amdblocks/espi.h
1 file changed, 15 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index 435b81f..82bfcbe 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -13,13 +13,23 @@
 #define  ESPI_DECODE_MMIO_RANGE_EN(range)	(1 << (((range) & 3) + 12))
 #define  ESPI_DECODE_IO_RANGE_EN(range)		(1 << (((range) & 3) + 8))
 #define  ESPI_DECODE_IO_0x80_EN			(1 << 2)
-#define  ESPI_DECODE_IO_0X60_0X64_EN	        (1 << 1)
+#define  ESPI_DECODE_IO_0X60_0X64_EN		(1 << 1)
 #define  ESPI_DECODE_IO_0X2E_0X2F_EN		(1 << 0)

-#define ESPI_IO_RANGE_BASE(range)		(0x44 + ((range) & 3) * 2)
-#define ESPI_IO_RANGE_SIZE(range)		(0x4c + ((range) & 3))
-#define ESPI_MMIO_RANGE_BASE(range)		(0x50 + ((range) & 3) * 4)
-#define ESPI_MMIO_RANGE_SIZE(range)		(0x60 + ((range) & 3) * 2)
+#define ESPI_IO_BASE_OFFSET_REG0		0x44
+#define ESPI_IO_BASE_OFFSET_REG1		0x48
+#define ESPI_IO_RANGE_SIZE_OFFSET		0x4c
+#define ESPI_MMIO_BASE_OFFSET_REG0		0x50
+#define ESPI_MMIO_BASE_OFFSET_REG1		0x54
+#define ESPI_MMIO_BASE_OFFSET_REG2		0x58
+#define ESPI_MMIO_BASE_OFFSET_REG3		0x5C
+#define ESPI_MMIO_OFFSET_SIZE_REG0		0x60
+#define ESPI_MMIO_OFFSET_SIZE_REG1		0x64
+
+#define ESPI_IO_RANGE_BASE(range)	(ESPI_IO_BASE_OFFSET_REG0 + ((range) & 3) * 2)
+#define ESPI_IO_RANGE_SIZE(range)	(ESPI_IO_RANGE_SIZE_OFFSET + ((range) & 3))
+#define ESPI_MMIO_RANGE_BASE(range)	(ESPI_MMIO_BASE_OFFSET_REG0 + ((range) & 3) * 4)
+#define ESPI_MMIO_RANGE_SIZE(range)	(ESPI_MMIO_OFFSET_SIZE_REG0 + ((range) & 3) * 2)

#define ESPI_GENERIC_IO_WIN_COUNT		4
 #define ESPI_GENERIC_IO_MAX_WIN_SIZE		0x100