Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21150

Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers
......................................................................

soc/intel/skylake: Usable dram top calculation based on HW registers

This patch ensures that entire system memory calculation is done
based on host bridge registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.

Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/skylake/memmap.c
2 files changed, 89 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21150/1

diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 52ef640..a7c159a 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -59,6 +59,15 @@
 /* CPU Trace reserved memory size */
 #define TRACE_MEMORY_SIZE	0x8000000	/* 128MiB */

+/* Probeless Trace memory size */
+#define GDXC_MOT_MEMORY_SIZE	0x6000000 /* 96MiB */
+#define GDXC_IOT_MEMORY_SIZE	0x2000000 /* 32MiB */
+#define PSMI_BUFFER_AREA_SIZE	0x4000000 /* 64MiB */
+
+/* PTT registers */
+#define PTT_TXT_BASE_ADDRESS	0xfed30800
+#define PTT_PRESENT		0x00070000
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 43faabb..34d2e10 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -17,8 +17,10 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <chip.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/smm.h>
@@ -106,6 +108,15 @@
    return 0;
 }

+static bool is_ptt_enable(void)
+{
+	if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
+			PTT_PRESENT)
+		return true;
+
+	return false;
+}
+
 /*
  * Host Memory Map:
  *
@@ -125,6 +136,8 @@
  * |    PRM (C6DRAM/SGX)      |
  * +--------------------------+ PRMRR
  * |     Trace Memory         |
+ * +--------------------------+ Probless Trace
+ * |     PTT                        |
  * +--------------------------+ top_of_ram
  * |     Reserved - FSP/CBMEM |
  * +--------------------------+ TOLUM
@@ -136,41 +149,84 @@
  * the base registers from each other to determine sizes of the regions. In
  * other words, the memory map is in a fixed order no matter what.
  */
+static u32 calculate_dram_base(void)
+{
+	const struct soc_intel_skylake_config *config;
+	const struct device *dev;
+	uint32_t tolud_base;
+	uint32_t dram_base;
+	uint32_t prmrr_base;
+	size_t prmrr_size;

+	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+
+	/* Read TOLUD from Host Bridge offset */
+	dram_base = tolud_base = sa_get_tolud_base();
+
+	if (dev->enabled) {
+		/* Read BDSM from Host Bridge */
+		dram_base -= sa_get_dsm_size();
+
+		/* Read BGSM from Host Bridge */
+		dram_base -= sa_get_gsm_size();
+	}
+	/* Get TSEG size */
+	dram_base -= smm_region_size();
+
+	/* Get DPR size */
+	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
+		dram_base -= sa_get_dpr_size();
+
+	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
+	config = dev->chip_info;
+	prmrr_size = config->PrmrrSize;
+
+	/*
+	 * PRMRR Sizes that are > 1MB and < 32MB are
+	 * not supported and will fail out.
+	 */
+	if ((prmrr_size > (1*MiB)) && (prmrr_size < (32*MiB)))
+		die("PRMRR Sizes that are > 1MB and < 32MB are not"
+				"supported!\n");
+
+	if (prmrr_size > 0) {
+		prmrr_base = dram_base - prmrr_size;
+		if (prmrr_size >= 32*MiB)
+			/* Make 128 MB align code */
+			prmrr_base &= ~(128*MiB - 1);
+		dram_base = prmrr_base;
+	}
+
+	if (config->ProbelessTrace) {
+		/* GDXC MOT */
+		dram_base -= GDXC_MOT_MEMORY_SIZE;
+		/* Round down to natual boundary accroding to PSMI size */
+		dram_base &= ~(PSMI_BUFFER_AREA_SIZE - 1);
+		/* GDXC IOT */
+		dram_base -= GDXC_IOT_MEMORY_SIZE;
+		/* PSMI buffer area */
+		dram_base -= PSMI_BUFFER_AREA_SIZE;
+	}
+
+	if (is_ptt_enable())
+		dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */
+
+	return dram_base;
+}
+
+/* Get usable system memory start address */
 static u32 top_of_32bit_ram(void)
 {
-	msr_t prmrr_base;
-	u32 top_of_ram;
-	const struct device *dev;
-	const struct soc_intel_skylake_config *config;
-
    /*
     * Check if Tseg has been initialized, we will use this as a flag
     * to check if the MRC is done, and only then continue to read the
     * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
     * PRMRR_MASK MSR lock bit is set.
     */
-	top_of_ram = smm_region_start();
-	if (top_of_ram == 0)
+	if (smm_region_start() == 0)
    	return 0;

-	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
-	config = dev->chip_info;
-
-	/*
-	 * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved
-	 * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB)
-	 * for PTT if enabled. PTT is in fact not used on Skylake platforms.
-	 * Refer to Fsp Integration Guide for the memory mapping layout.
-	 */
-	prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
-	if (prmrr_base.lo)
-		top_of_ram = prmrr_base.lo;
-
-	if (config->ProbelessTrace)
-		top_of_ram -= TRACE_MEMORY_SIZE;
-
-	return top_of_ram;
+	return calculate_dram_base();
 }

void *cbmem_top(void)