Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps ......................................................................
[WIP] nb/intel/haswell/pcie.c: Add some ASPM steps
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/pcie.c 1 file changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/1
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index d9e77a7..6eba75e 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -5,6 +5,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <assert.h>
static void pcie_disable(struct device *dev) @@ -13,6 +14,17 @@ dev->enabled = 0; }
+static void pcie_init(struct device *dev) +{ + /* Enable support for L0s and L1 */ + pci_or_config32(dev, 0xac, 3 << 10); + + pci_and_config32(dev, 0x200, ~(3 << 26)); + + /* Other fields in the register must not be changed while writing this */ + pci_or_config16(dev, 0x258, 1 << 2); +} + #if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { @@ -54,7 +66,7 @@ .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, .disable = pcie_disable, - .init = pci_dev_init, + .init = pcie_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name,
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47223
to look at the new patch set (#5).
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Tested on Asrock B85M Pro4, registers now have the expected values.
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/pcie.c 2 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/5
Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/e3522d55_b877df49 PS5, Line 9: expected How do you know, what values are expected?
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/e1ecbea0_19ac7ecd PS5, Line 9: expected
How do you know, what values are expected?
Documentation and/or reference code lists the configuration steps that "BIOS" needs to do. After implementing these steps in coreboot, I expect that the registers contain the values I've programmed them to.
I'll update the commit message.
Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/995e7541_638aa055 PS6, Line 8: Is this currently done by MRC? not done at all?
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/814aeecb_c99719be PS6, Line 33: 0x11a Datasheet says 0x114 (0x11a is status)? BIOS spec too.
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/100b484b_fc83e1d3 PS6, Line 62: slotcap |= func << 19; BIOS spec says this should be unique. In case MRC does something similar to the PCH root ports, it would be good to document the numbering scheme. In case it doesn't, I'd prefer to leave it 0 until we want to program it properly (see below).
I guess this should actually be decided by the devicetree of the mainboard. PCIe spec says:
"This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port."
IOW, we shouldn't set this >0 if there is no physical slot. And also initializing it with the function number may lead to a spurious 0.
https://review.coreboot.org/c/coreboot/+/47223/comment/6e4331ce_2a36de9f PS6, Line 68: /* 75 watts power limit */ How to know if that's true for a board?
https://review.coreboot.org/c/coreboot/+/47223/comment/779ae947_cb7835c6 PS6, Line 69: 0x3ff `0xff` (the rest is already set above)
https://review.coreboot.org/c/coreboot/+/47223/comment/4da106c9_66f60300 PS6, Line 75: or No need to read, just pci_write_config16() would do.
https://review.coreboot.org/c/coreboot/+/47223/comment/5ad83aba_d0b99d68 PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19); Hmm, BIOS spec says to lock (read, write) the original value.
https://review.coreboot.org/c/coreboot/+/47223/comment/589383ef_9d06b382 PS6, Line 109: 0xac Should be LCAP?
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/c6adfc08_470a5e9e PS6, Line 8:
Is this currently done by MRC? not done at all?
It wasn't done at all, IIRC. I can re-check.
Patchset:
PS6: a
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/42400452_cc15a169 PS6, Line 33: 0x11a
Datasheet says 0x114 (0x11a is status)? […]
Oops, well-spotted.
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/81ee10e9_ee7fabac PS6, Line 68: /* 75 watts power limit */
How to know if that's true for a board?
Devicetree, probably. i945 also has a FIXME.
https://review.coreboot.org/c/coreboot/+/47223/comment/b88302a8_0f74684a PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
Hmm, BIOS spec says to lock (read, write) the original value.
What's the date of the BIOS spec? I can disable OBFF if need be.
https://review.coreboot.org/c/coreboot/+/47223/comment/6639f904_0ab94e35 PS6, Line 109: 0xac
Should be LCAP?
Yes, most likely
Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(1 comment)
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/d0d49017_8cfe8304 PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
What's the date of the BIOS spec? I can disable OBFF if need be.
This was March 2014, 1.8.0. I'll check if there's an update.
Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(1 comment)
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/d47d49d9_b665aafb PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
This was March 2014, 1.8.0. I'll check if there's an update.
Nothing new. Anyway, if you are sure that other code forces it to 1, that's ok, just wanted to check.
Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47223
to look at the new patch set (#7).
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Tested on Asrock B85M Pro4, registers now have the expected values.
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/pcie.c 3 files changed, 118 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/7
Attention is currently required from: Paul Menzel, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47223
to look at the new patch set (#8).
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Add devicetree configuration parameters for mainboard-specific settings, and provide reasonable defaults, which should usually be good enough.
Tested on Asrock B85M Pro4, registers now have the expected values.
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/pcie.c 3 files changed, 125 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/8
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(6 comments)
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/9f759562_8891a71d PS6, Line 33: 0x11a
Oops, well-spotted.
Done
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/10d2b3c7_37128a5d PS6, Line 62: slotcap |= func << 19;
BIOS spec says this should be unique. In case MRC does something […]
For now, I've initialised the port number using `func + 1`, which matches what vendor firmware does. I've added devicetree options, in case someone wants to adjust this.
Oh, and I need to update the Slot Implemented bit for onboard devices. Reference code always sets this bit, but apparently it's R/WO.
https://review.coreboot.org/c/coreboot/+/47223/comment/dd2b2e73_b976c6e8 PS6, Line 68: /* 75 watts power limit */
Devicetree, probably. i945 also has a FIXME.
Reference code hardcodes 75 W. I've added devicetree options in case someone wants to override this, but I doubt anyone will use them.
https://review.coreboot.org/c/coreboot/+/47223/comment/8160845f_b96a9589 PS6, Line 69: 0x3ff
`0xff` (the rest is already set above)
Done
https://review.coreboot.org/c/coreboot/+/47223/comment/98f3ccb1_540f7c1a PS6, Line 75: or
No need to read, just pci_write_config16() would do.
Done
https://review.coreboot.org/c/coreboot/+/47223/comment/4bd0c6d0_97a367d1 PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
Nothing new. Anyway, if you are sure that other code forces it to 1, that's […]
Interesting. Vendor firmware on a Toshiba Satellite Pro L70-A enables OBFF. I'll leave this as-is.
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/aa9b44a9_a0475715 PS6, Line 8:
It wasn't done at all, IIRC. I can re-check.
Reference code does this in DXE, and MRC does not contain DXE code. So, no.
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47223
to look at the new patch set (#9).
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Add devicetree configuration parameters for mainboard-specific settings, and provide reasonable defaults, which should usually be good enough. This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014).
Tested on Asrock B85M Pro4, registers now have the expected values.
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/pcie.c 3 files changed, 125 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/9
Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/0b48818d_5703c5bb PS5, Line 9: expected
Documentation and/or reference code lists the configuration steps that "BIOS" needs to do. […]
Done
Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 9: Code-Review+2
(2 comments)
Patchset:
PS9: I forgot two times during review that it's about PEG (i.e. not the PCH RPs). Defaults makes sense for PEG! ^^
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/32072c08_d14c213b PS9, Line 23: #define PEG_CAP 0xa2 I just realized, most of these are PCIe standard anyway, just the base offset is implementation specific. Here, everything is +0xa0. e.g.
PEG_CAP == 0xa0 + PCI_EXP_FLAGS, PEG_DCAP == 0xa0 + PCI_EXP_DEVCAP
etc.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Add devicetree configuration parameters for mainboard-specific settings, and provide reasonable defaults, which should usually be good enough. This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014).
Tested on Asrock B85M Pro4, registers now have the expected values.
Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47223 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/pcie.c 3 files changed, 125 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 99102b6..274e549 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -4,6 +4,14 @@ #define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
#include <drivers/intel/gma/gma.h> +#include <types.h> + +struct peg_config { + bool is_onboard; + uint8_t power_limit_scale; + uint8_t power_limit_value; + uint16_t phys_slot_number; +};
/* * Digital Port Hotplug Enable: @@ -20,6 +28,8 @@ /* IGD panel configuration */ struct i915_gpu_panel_config panel_cfg;
+ struct peg_config peg_cfg[3]; + bool gpu_ddi_e_connected;
bool ec_present; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f158c21..b6c2b5f 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -20,12 +20,33 @@
/* Device 0:1.0 PCI configuration space (PCIe Graphics) */
+#define PEG_CAP 0xa2 +#define PEG_DCAP 0xa4 + +#define PEG_LCAP 0xac + +#define PEG_DSTS 0xaa + +#define PEG_SLOTCAP 0xb4 + #define PEG_DCAP2 0xc4 /* 32bit */
+#define PEG_LCTL2 0xd0 + +#define PEG_VC0RCTL 0x114 + #define PEG_ESD 0x144 /* 32bit */ #define PEG_LE1D 0x150 /* 32bit */ #define PEG_LE1A 0x158 /* 64bit */
+#define PEG_UESTS 0x1c4 +#define PEG_UESEV 0x1cc +#define PEG_CESTS 0x1d0 + +#define PEG_L0SLAT 0x22c + +#define PEG_AFE_PM_TMR 0xc28 + /* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */ diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index a631cc8..ac6d4ca 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -5,7 +5,12 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <assert.h> +#include <types.h> + +#include "chip.h" +#include "haswell.h"
#if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) @@ -41,12 +46,101 @@ } #endif
+static void peg_enable(struct device *dev) +{ + const struct northbridge_intel_haswell_config *config = config_of(dev); + + const uint8_t func = PCI_FUNC(PCI_BDF(dev)); + + assert(func < ARRAY_SIZE(config->peg_cfg)); + + const bool slot_implemented = !config->peg_cfg[func].is_onboard; + + if (slot_implemented) { + /* Default is 1, but register is R/WO and needs to be written to once */ + pci_or_config16(dev, PEG_CAP, 1 << 8); + } else { + pci_and_config16(dev, PEG_CAP, ~(1 << 8)); + } + + /* Note: this register is write-once */ + uint32_t slotcap = pci_read_config32(dev, PEG_SLOTCAP); + + /* Physical slot number (zero for ports connected to onboard devices) */ + slotcap &= ~(0x1fff << 19); + if (slot_implemented) { + uint16_t slot_number = config->peg_cfg[func].phys_slot_number & 0x1fff; + if (slot_number == 0) { + /* Slot number must be non-zero and unique */ + slot_number = func + 1; + } + slotcap |= slot_number << 19; + } + + /* Default to 1.0 watt scale */ + slotcap &= ~(3 << 15); + slotcap |= (config->peg_cfg[func].power_limit_scale & 3) << 15; + + uint8_t power_limit_value = config->peg_cfg[func].power_limit_value; + if (power_limit_value == 0) { + /* Default to 75 watts */ + power_limit_value = 75; + } + slotcap &= ~(0xff << 7); + slotcap |= power_limit_value << 7; + + pci_write_config32(dev, PEG_SLOTCAP, slotcap); + + /* Clear errors */ + pci_write_config16(dev, PCI_STATUS, 0xffff); + pci_write_config16(dev, PCI_SEC_STATUS, 0xffff); + pci_write_config16(dev, PEG_DSTS, 0xffff); + pci_write_config32(dev, PEG_UESTS, 0xffffffff); + pci_write_config32(dev, PEG_CESTS, 0xffffffff); + pci_write_config32(dev, 0x1f0, 0xffffffff); + + pci_or_config32(dev, PEG_VC0RCTL, 0x7f << 1); + + /* Advertise OBFF support using WAKE# signaling only */ + pci_or_config32(dev, PEG_DCAP2, 1 << 19); + + pci_or_config32(dev, PEG_UESEV, 1 << 14); + + /* Select -3.5 dB de-emphasis */ + pci_or_config32(dev, PEG_LCTL2, 1 << 6); + + pci_or_config32(dev, PEG_L0SLAT, 1 << 31); + + pci_update_config32(dev, 0x250, ~(7 << 20), 2 << 20); + + pci_or_config32(dev, 0x238, 1 << 29); + + pci_or_config32(dev, 0x1f8, 1 << 16); + + pci_update_config32(dev, PEG_AFE_PM_TMR, ~0x1f, 0x13); + + /* Lock DCAP */ + pci_update_config32(dev, PEG_DCAP, ~0, 0); + + if (func == 0) + pci_or_config32(dev, 0xcd0, 1 << 11); + + /* Enable support for L0s and L1 */ + pci_or_config32(dev, PEG_LCAP, 3 << 10); + + pci_and_config32(dev, 0x200, ~(3 << 26)); + + /* Other fields in this register must not be changed while writing this */ + pci_or_config16(dev, 0x258, 1 << 2); +} + static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, + .enable = peg_enable, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES)
Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10: This patch has something to do with https://ticket.coreboot.org/issues/310. Does this work when devicetree enables PEG but the device on PEG is not present?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
This patch has something to do with https://ticket.coreboot.org/issues/310. […]
This can happen when a PEG function exists but is not present in the devicetree. Let me relax the `config_of()`.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
This can happen when a PEG function exists but is not present in the devicetree. […]
Actually, something seems to be going very wrong in this board-status log: https://review.coreboot.org/plugins/gitiles/board-status/+/refs/heads/master...
00:01.0 is disabled, but 00:01.1 remains enabled. I'll also make patches to disable 00:01.1 in the devicetree.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Actually, something seems to be going very wrong in this board-status log: https://review.coreboot. […]
https://review.coreboot.org/q/topic:%22haswell-peg-woes%22
-
Angel Pons (Code Review) -
Iru Cai (vimacs) (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)