Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47888 )
Change subject: sb/intel/ibexpeak: Simplify SATA RMW operations ......................................................................
sb/intel/ibexpeak: Simplify SATA RMW operations
Change-Id: I115cb45b7573c8c9057ad0b7951cd0b3a79a1200 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/ibexpeak/sata.c 1 file changed, 4 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47888/1
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 20458f5..2072730 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -65,10 +64,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8100 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* 6 ports SKU + ORM */ + pci_update_config16(dev, 0x92, ~0x3f, 0x8100 | config->sata_port_map);
/* SATA Initialization register */ pci_write_config32(dev, 0x94, @@ -123,9 +120,7 @@ pci_write_config32(dev, 0x24, 0x00000000);
/* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
/* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -141,10 +136,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map);
/* SATA Initialization register */ pci_write_config32(dev, 0x94,
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47888?usp=email )
Change subject: sb/intel/ibexpeak: Simplify SATA RMW operations ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Martin L Roth (Code Review)