[S] Change in coreboot[main]: soc/intel/adl: Handle critical low battery early in romstage

[Julius Werner (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86227?usp=email )

Change subject: soc/intel/adl: Handle critical low battery early in romstage
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/86227/comment/e6ee13ae_1341a45b?usp... :
PS3, Line 446: 			early_shutdown_if_battery_below_critical_threshold();
> I think the motivation is to inform the user as much as possible through Graphical UI than text. […]

Oh, okay, so this isn't mutually exclusive with the ramstage version, this is only for the memory training / CSE update case, and in all other cases we want to wait until ramstage. That really isn't obvious from the code yet, it would be good to add a comment and expand the Kconfig help description to explain that more clearly.