Hello Shreesh Chhabbi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/43276
to review the following change.
Change subject: md/tgl: Enable SaGv for TGL-U RVP ......................................................................
md/tgl: Enable SaGv for TGL-U RVP
Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43276/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4010772..ff3c96c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,7 @@ register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: md/tgl: Enable SaGv for TGL-U RVP ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43276/1//COMMIT_MSG@8 PS1, Line 8: Can you add test info?
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43276
to look at the new patch set (#2).
Change subject: md/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
md/tgl: Enable SaGv for TGL-UP3 RVP
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully.
Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43276/2
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: md/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
Patch Set 2:
Please help to review.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: md/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43276/1//COMMIT_MSG@8 PS1, Line 8:
Can you add test info?
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: md/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43276/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43276/2//COMMIT_MSG@7 PS2, Line 7: md mb
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: md/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Jyotsna Shridharan, Francois Toguo Fotso, Wonkyu Kim, Ravishankar Sarawadi, Duncan Laurie, Angel Pons, Shreesh Chhabbi, Jamie Ryu, Caveh Jalali, Nick Vaccaro, Raj Astekar, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43276
to look at the new patch set (#3).
Change subject: mb/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
mb/tgl: Enable SaGv for TGL-UP3 RVP
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully.
Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43276/3
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: mb/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43276/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43276/2//COMMIT_MSG@7 PS2, Line 7: md
mb
Done
Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43276 )
Change subject: mb/tgl: Enable SaGv for TGL-UP3 RVP ......................................................................
mb/tgl: Enable SaGv for TGL-UP3 RVP
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully.
Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5d4d246..2dd65c4 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,7 @@ register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
-
Angel Pons (Code Review) -
Duncan Laurie (Code Review)
-
Nick Vaccaro (Code Review)
-
Shreesh Chhabbi (Code Review)
-
Wonkyu Kim (Code Review)