Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

[Sumeet R Pawnikar (Code Review)]

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Rocky Phagura, Arthur Heymans, Morgan Jang, Patrick Rudolph.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55098 )

Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
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Patch Set 2:

(2 comments)

File src/soc/intel/xeon_sp/cpx/cpu.c:

https://review.coreboot.org/c/coreboot/+/55098/comment/12ead1e0_975f0688 
PS2, Line 26: #include <soc/pci_devs.h>
Please add this in alphabetical order, for an example after line 21.

https://review.coreboot.org/c/coreboot/+/55098/comment/03e5daee_ae6f4349 
PS2, Line 109: /*
             : 	 * The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
             : 	 * Lock Turbo. Did FSP-S set this up???
             : 	 */
You might want to use the concise style as below:
/* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
   Lock Turbo. Did FSP-S set this up??? */