Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM

[Paul Menzel (Code Review)]

Attention is currently required from: Tarun Tuli.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 )

Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
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Patch Set 8:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/63969/comment/c0f50773_f6d43720 
PS8, Line 9: Implement sub-function 1 (Get Device Constraints)
           : of the Low Power S0 Idle Device-Specific Method (_DSM).
           : This provides a way in which to describe various devices required
           : D-states to enter LPM (S0ix).  The information can be used to help in
           : diagnostics and understanding of S0ix entry failure.
           : 
           : This implementation adds support for ADL.  Other SoC's could be
           : ported to be included as well.  If they aren't, they will default to
           : the existing behavior of a single hardcoded device to ensure compatibility
           : with Windows.
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