Change in coreboot[master]: soc/intel/tigerlake: Match RP number with TGL EDS

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39490 )

Change subject: soc/intel/tigerlake: Match RP number with TGL EDS
......................................................................

soc/intel/tigerlake: Match RP number with TGL EDS

Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.

BUG=b:151208838
TEST=build RVP successfully

Signed-off-by: Wonkyu Kim 
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
---
M src/soc/intel/tigerlake/acpi/pcie.asl
1 file changed, 0 insertions(+), 67 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/39490/1

diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 0191454..63e4d84 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -313,70 +313,3 @@
    }
 }

-Device (RP13)
-{
-	Name (_ADR, 0x001D0004)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP14)
-{
-	Name (_ADR, 0x001D0005)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP15)
-{
-	Name (_ADR, 0x001D0006)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP16)
-{
-	Name (_ADR, 0x001D0007)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39490

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Match RP number with TGL EDS
......................................................................

soc/intel/tigerlake: Match RP number with TGL EDS

Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.

BUG=b:151208838
TEST=build RVP successfully

Signed-off-by: Wonkyu Kim 
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
---
M src/soc/intel/tigerlake/acpi/pcie.asl
1 file changed, 0 insertions(+), 68 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/39490/2

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39490 )

Change subject: soc/intel/tigerlake: Match RP number with TGL EDS
......................................................................

Patch Set 2: Code-Review+1

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39490 )

Change subject: soc/intel/tigerlake: Match RP number with TGL EDS
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39490 )

Change subject: soc/intel/tigerlake: Match RP number with TGL EDS
......................................................................

soc/intel/tigerlake: Match RP number with TGL EDS

Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.

BUG=b:151208838
TEST=build RVP successfully

Signed-off-by: Wonkyu Kim 
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) 
Reviewed-by: Caveh Jalali 
Reviewed-by: Srinidhi N Kaushik 
---
M src/soc/intel/tigerlake/acpi/pcie.asl
1 file changed, 0 insertions(+), 68 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Srinidhi N Kaushik: Looks good to me, approved
  Caveh Jalali: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 0191454..c6cfbce 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -312,71 +312,3 @@
    	Return (IRQM (RPPN))
    }
 }
-
-Device (RP13)
-{
-	Name (_ADR, 0x001D0004)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP14)
-{
-	Name (_ADR, 0x001D0005)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP15)
-{
-	Name (_ADR, 0x001D0006)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP16)
-{
-	Name (_ADR, 0x001D0007)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}