Change in coreboot[master]: soc/intel/smm: Disable xHCI before going to S5

[Felix Singer (Code Review)]

Hello Nico Huber,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/39831

to review the following change.

Change subject: soc/intel/smm: Disable xHCI before going to S5
......................................................................

soc/intel/smm: Disable xHCI before going to S5

Change-Id: I986a0a14e44cb67eeb6e3368317a9e5411aa7475
Signed-off-by: Nico Huber 
---
M src/soc/intel/common/block/smm/smihandler.c
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39831/1

diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index af1c633..f6ad0aa 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -34,6 +34,7 @@
 #include <soc/pm.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
+#include <soc/pci_devs.h>
 #include <soc/smbus.h>
 #include <spi-generic.h>
 #include <stdint.h>
@@ -189,6 +190,23 @@
    }
 }

+static void xhci_stop(void)
+{
+	if (pci_read_config32(PCH_DEV_XHCI, PCI_VENDOR_ID) == 0xffffffff)
+		return;
+
+	if ((pci_read_config32(PCH_DEV_XHCI, PCI_COMMAND) & PCI_COMMAND_MEMORY) == 0)
+		return;
+
+	/* BAR above 4GiB is not supported here. */
+	if (pci_read_config32(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0 + 4) != 0)
+		return;
+
+	const uintptr_t mmio = pci_read_config32(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0)
+				& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	/* Clear Run/Stop (RS) bit. */
+	write32((void *)(mmio + 0x80), read32((void *)(mmio + 0x80)) & ~1);
+}

void smihandler_southbridge_sleep(
    const struct smm_save_state_ops *save_state_ops)
@@ -233,6 +251,8 @@
    case ACPI_S5:
    	printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");

+		/* Quirk handling for xHCI not shutting down properly. */
+		xhci_stop();
    	/* Disable all GPE */
    	pmc_disable_all_gpe();
    	/* Set which state system will be after power reapplied */