[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping

[Mac Chiang (Code Review)]

Mac Chiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email )

Change subject: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping
......................................................................

mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping

The DMIC_CLK_A1 and DMIC_DAT_A1 function pins on GPP_D16 and GPP_D17
are configured to NF3.

BUG=b:378629979
Test=emerge-fatcat coreboot
Verify DMIC recording functionality.
Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav

Signed-off-by: Mac Chiang 
Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928
---
M src/mainboard/google/fatcat/variants/felino/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/87237/1

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 3b2a693..a70e9fe 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -182,9 +182,9 @@
    /* GPP_D15:     NC */
    PAD_NC(GPP_D15, NONE),
    /* GPP_D16:     PCH_DMIC_CLK1 */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
    /* GPP_D17:     PCH_DMIC_DATA1 */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
    /* GPP_D18:     PCIE_CLKREQ_SD_N */
    PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
    /* GPP_D19:     NC */