Change in ...coreboot[master]: WIP: mb/google/sarien/variants: Add DPTF based Fan control - coreboot-gerrit

7 Jan 2019

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30700
Change subject: WIP: mb/google/sarien/variants: Add DPTF based Fan control
......................................................................
WIP: mb/google/sarien/variants: Add DPTF based Fan control
Add DPTF based Fan speed control support for WHL based
Sarien and Arcada systems.
Change-Id: I4a8a30bcfe1e05a7ff3bdc7fabcd059112c23046
Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com
---
M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
2 files changed, 118 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30700/1

diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
index 2d35878..1a9419a 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
@@ -15,20 +15,78 @@
#define DPTF_CPU_PASSIVE	80
 #define DPTF_CPU_CRITICAL	100
+#define DPTF_CPU_ACTIVE_AC0	87
+#define DPTF_CPU_ACTIVE_AC1	85
+#define DPTF_CPU_ACTIVE_AC2	83
+#define DPTF_CPU_ACTIVE_AC3	80
+#define DPTF_CPU_ACTIVE_AC4	75
#define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Thermal 1"
 #define DPTF_TSR0_PASSIVE	55
 #define DPTF_TSR0_CRITICAL	80
+#define DPTF_TSR0_ACTIVE_AC0	50
+#define DPTF_TSR0_ACTIVE_AC1	47
+#define DPTF_TSR0_ACTIVE_AC2	45
+#define DPTF_TSR0_ACTIVE_AC3	42
+#define DPTF_TSR0_ACTIVE_AC4	39
#define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"Thermal 2"
 #define DPTF_TSR1_PASSIVE	55
 #define DPTF_TSR1_CRITICAL	80
+#define DPTF_TSR1_ACTIVE_AC0	50
+#define DPTF_TSR1_ACTIVE_AC1	47
+#define DPTF_TSR1_ACTIVE_AC2	45
+#define DPTF_TSR1_ACTIVE_AC3	42
+#define DPTF_TSR1_ACTIVE_AC4	39
-#undef DPTF_ENABLE_FAN_CONTROL
+#define DPTF_ENABLE_FAN_CONTROL
 #undef DPTF_ENABLE_CHARGER
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *        These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,         0xFFFFFFFF,     6700,   220,    2200},
+	Package () {80,         0xFFFFFFFF,     5800,   180,    1800},
+	Package () {70,         0xFFFFFFFF,     5000,   145,    1450},
+	Package () {60,         0xFFFFFFFF,     4900,   115,    1150},
+	Package () {50,         0xFFFFFFFF,     3838,   90,     900},
+	Package () {40,         0xFFFFFFFF,     2904,   55,     550},
+	Package () {30,         0xFFFFFFFF,     2337,   30,     300},
+	Package () {20,         0xFFFFFFFF,     1608,   15,     150},
+	Package () {10,         0xFFFFFFFF,     800,    10,     100},
+	Package () {0,          0xFFFFFFFF,     0,      0,      50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,      // Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *      AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	}
+})
+#endif
+
 Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
    Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
index 2d35878..d416285 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -15,20 +15,78 @@
#define DPTF_CPU_PASSIVE	80
 #define DPTF_CPU_CRITICAL	100
+#define DPTF_CPU_ACTIVE_AC0	87
+#define DPTF_CPU_ACTIVE_AC1	85
+#define DPTF_CPU_ACTIVE_AC2	83
+#define DPTF_CPU_ACTIVE_AC3	80
+#define DPTF_CPU_ACTIVE_AC4	75
#define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Thermal 1"
 #define DPTF_TSR0_PASSIVE	55
 #define DPTF_TSR0_CRITICAL	80
+#define DPTF_TSR0_ACTIVE_AC0	50
+#define DPTF_TSR0_ACTIVE_AC1	47
+#define DPTF_TSR0_ACTIVE_AC2	45
+#define DPTF_TSR0_ACTIVE_AC3	42
+#define DPTF_TSR0_ACTIVE_AC4	39
#define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"Thermal 2"
 #define DPTF_TSR1_PASSIVE	55
 #define DPTF_TSR1_CRITICAL	80
+#define DPTF_TSR1_ACTIVE_AC0	50
+#define DPTF_TSR1_ACTIVE_AC1	47
+#define DPTF_TSR1_ACTIVE_AC2	45
+#define DPTF_TSR1_ACTIVE_AC3	42
+#define DPTF_TSR1_ACTIVE_AC4	39
-#undef DPTF_ENABLE_FAN_CONTROL
+#define DPTF_ENABLE_FAN_CONTROL
 #undef DPTF_ENABLE_CHARGER
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	}
+})
+#endif
+
 Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
    Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4a8a30bcfe1e05a7ff3bdc7fabcd059112c23046
Gerrit-Change-Number: 30700
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com
Gerrit-MessageType: newchange



    