Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/1

diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
index 82d632e..652cbab 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
@@ -12,6 +12,7 @@
 #include <stdint.h>
 #include <fsp/soc_binding.h>

+#define DIMMS_PER_CHANNEL	2
 #define BYTES_PER_CHANNEL	2
 #define BITS_PER_BYTE		8
 #define DQ_PER_CHANNEL		(BYTES_PER_CHANNEL * BITS_PER_BYTE)
@@ -20,8 +21,13 @@

#define LPDDR4X_CHANNELS	8

+#define DDR4_CHANNELS		2
+#define DDR4_DIMM_SLOTS	(DIMMS_PER_CHANNEL * DDR4_CHANNELS)
+
 enum mem_topology {
    MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */
+	SODIMM, /* Supports reading SPD using SMBus. */
+	MIXED,  /* Only DDR4 supports this (CH0 = MD, CH1 = SODIMM) */
 };

enum md_spd_loc {
@@ -44,6 +50,9 @@
    	uintptr_t data_ptr;
    	size_t data_len;
    };
+
+	/* SPD info for SODIMM topology */
+	uint8_t smbus_addr[DDR4_DIMM_SLOTS];
 };

/* Board-specific memory configuration information */

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 2: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 29: /* Supports reading SPD using SMBus. */
nit: line these comments up with MEMORY_DOWN

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 25: #define DDR4_DIMM_SLOTS	(DIMMS_PER_CHANNEL * DDR4_CHANNELS)
nits: one more tab, align with above.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 25: #define DDR4_DIMM_SLOTS	(DIMMS_PER_CHANNEL * DDR4_CHANNELS)
> nits: one more tab, align with above.

Done

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 29: /* Supports reading SPD using SMBus. */
> nit: line these comments up with MEMORY_DOWN

Done

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/3

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/4

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 4: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 5: Code-Review+2

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/7

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 8: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 8: Code-Review+2

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#11).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/11

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 11:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 25: s(
nit: space

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 54: SMBUS
addr_dimmN or say leave the smbus address as 0?

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#12).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/12

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 11:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 25: s(
> nit: space

Done

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 54: SMBUS
> addr_dimmN or say leave the smbus address as 0?

Woops. Thanks for catching that.

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 12:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
PS12, Line 57: 		/* SMBUS address for DIMM0 within the channel. */
nit: SMBus

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
PS12, Line 59: 		/* SMBUS address for DIMM1 within the channel. */
same.

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#13).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/13

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 13:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
PS12, Line 57: 		/* SMBUS address for DIMM0 within the channel. */
> nit: SMBus

Done

https://review.coreboot.org/c/coreboot/+/39866/12/src/soc/intel/tigerlake/in... 
PS12, Line 59: 		/* SMBUS address for DIMM1 within the channel. */
> same.

Done

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 13: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866
Tested-by: build bot (Jenkins) 
Reviewed-by: EricR Lai 
---
M src/soc/intel/tigerlake/include/soc/meminit.h
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h
index aab155e..a2fb3f4 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit.h
@@ -17,8 +17,13 @@
 #define LPDDR4X_CHANNELS		8
 #define LPDDR4X_BYTES_PER_CHANNEL	2

+#define DDR4_CHANNELS			2
+#define DDR4_BYTES_PER_CHANNEL		8
+
 enum mem_topology {
    MEMORY_DOWN,	/* Supports reading SPD from CBFS or in-memory pointer. */
+	SODIMM,		/* Supports reading SPD using SMBus (only for DDR4). */
+	MIXED,		/* CH0 = MD, CH1 = SODIMM (only for DDR4). */
 };

enum md_spd_loc {
@@ -43,6 +48,17 @@
    		size_t data_len;
    	};
    };
+
+	/*
+	 * SPD info for SODIMM topology.
+	 * Leave addr_dimmN as 0 for any DIMMs that are not populated.
+	 */
+	struct {
+		/* SMBus address for DIMM0 within the channel. */
+		uint8_t addr_dimm0;
+		/* SMBus address for DIMM1 within the channel. */
+		uint8_t addr_dimm1;
+	} smbus_info[DDR4_CHANNELS];
 };

/* Board-specific memory configuration information */

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 15:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2004
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2003
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2002

Please note: This test is under development and might not be accurate at all!