Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets

[Furquan Shaikh (Code Review)]

Attention is currently required from: Martin Roth, Karthik Ramasubramanian.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )

Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
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Patch Set 2:

(1 comment)

File src/mainboard/google/guybrush/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/52115/comment/e3e62ae2_8ee375de 
PS1, Line 54: HIGH
> Just for my own knowledge, what's the correct way to handle these timings constraints? The i2c ACPI  […]

Since FSP/AGESA is the one that is configuring the PCIE root ports, these timing constraints need to be handled in coreboot (bootblock or romstage). It actually depends on the hardware design as well. If there are no separate power enables for a device e.g. if PP3300_NVME is driven high by S0 rail, then all we need to do for SSD_AUX_RESET_L is ensure it gets deasserted 'x' ms from S0 rail going high. However, if there is a power enable which is under software control, then we need more logic for meeting the timing constraints. One way to handle this is adding enable GPIO control in bootblock and reset deassertion in romstage. Or adding explicit calls to mdelay() if more delay is required.