Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Drop reg-script for SA lockdown ......................................................................
soc/intel/broadwell: Drop reg-script for SA lockdown
We can just use proper code instead.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 25 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/1
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index bec62fb..1c5423c 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,6 +3,8 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <device/device.h> +#include <device/pci_ops.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> @@ -13,33 +15,6 @@ #include <soc/systemagent.h> #include <southbridge/intel/common/spi.h>
-const struct reg_script system_agent_finalize_script[] = { - REG_PCI_OR16(0x50, 1 << 0), /* GGC */ - REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ - REG_PCI_OR32(0x78, 1 << 10), /* ME */ - REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */ - REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */ - REG_PCI_OR32(0xa0, 1 << 0), /* TOM */ - REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */ - REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */ - REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ - REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ - REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), - REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ - - REG_SCRIPT_END -}; - const struct reg_script pch_finalize_script[] = { #if !CONFIG(SPI_CONSOLE) /* Lock SPIBAR */ @@ -74,7 +49,29 @@
printk(BIOS_DEBUG, "Finalizing chipset.\n");
- reg_script_run_on_dev(sa_dev, system_agent_finalize_script); + pci_or_config16(sa_dev, 0x50, 1 << 0); /* GGC */ + pci_or_config32(sa_dev, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(sa_dev, 0x78, 1 << 10); /* ME */ + pci_or_config32(sa_dev, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(sa_dev, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(sa_dev, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(sa_dev, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(sa_dev, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(sa_dev, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(sa_dev, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(sa_dev, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32(0x5500) |= (1 << 0); /* PAVP */ + MCHBAR32(0x5f00) |= (1 << 31); /* SA PM */ + MCHBAR32(0x6020) |= (1 << 0); /* UMA GFX */ + MCHBAR32(0x63fc) |= (1 << 0); /* VTDTRK */ + MCHBAR32(0x6800) |= (1 << 31); + MCHBAR32(0x7000) |= (1 << 31); + MCHBAR32(0x7ffc) |= (1 << 0); + MCHBAR32(0x5880) |= (1 << 5); /* DDR PTM */ + + /* Memory Controller Lockdown */ + MCHBAR8(0x50fc) = 0x8f;
spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Drop reg-script for SA lockdown ......................................................................
Patch Set 1: Code-Review+1
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
There's no need to use reg-script for this. Plus, some registers are written twice, which makes no sense. Revise the locking steps as per the Broadwell BIOS specification, and put names to MCHBAR registers.
The resulting sequence is nearly identical to the one for Haswell.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/include/soc/systemagent.h 2 files changed, 62 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 4:
(1 comment)
This would be a lot easier to review if you wouldn't change semantics and introduce macros in the same patch. Macro names that I also can't review because I can't find them in docs (and the limited code in coreboot provides no hint if the names make sense).
https://review.coreboot.org/c/coreboot/+/46324/4/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/4/src/soc/intel/broadwell/fin... PS4, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), Just kill it? ;)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 4:
Patch Set 4:
(1 comment)
This would be a lot easier to review if you wouldn't change semantics and introduce macros in the same patch. Macro names that I also can't review because I can't find them in docs (and the limited code in coreboot provides no hint if the names make sense).
Good point. I'll split up the actual "revise" part from the "use macros" part
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46324
to look at the new patch set (#5).
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
Some registers are written twice, which makes no sense. Revise the System Agent locking code as per the Broadwell BIOS specification. The resulting sequence is nearly identical to the one for Haswell.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 15 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46324/4/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/4/src/soc/intel/broadwell/fin... PS4, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
Just kill it? ;)
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46324/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46324/5//COMMIT_MSG@10 PS5, Line 10: as per the Broadwell BIOS specification sequence order looks much different though
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), Maybe you mixed up the numbers? This is 0x7*f*fc
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 38: REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ BIOS spec places this before 0x6800.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
Maybe you mixed up the numbers? This is 0x7*f*fc
D'oh
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46324
to look at the new patch set (#6).
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
Some registers were written to twice, and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted in ascending order for the sake of clarity.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
D'oh
D'oh-ne
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 38: REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
BIOS spec places this before 0x6800.
This is the memory controller lock register. It should have been written by MRC already, and does not depend on the other lock bits. I'll keep the registers sorted in increasing offset values.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46324/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46324/6//COMMIT_MSG@11 PS6, Line 11: for the sake of clarity How?
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ What happens here?
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 16: /* : * 16.6 System Agent Configuration Locking : * "5th Generation Intel Core Processor Family BIOS Specification" : * Document Number 535094 : * Revision 2.2.0, August 2014 : */ To be helpful, this needs additional comments when and why we deviate from the sequence in there.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
What happens here?
This register was dropped from the lockdown sequence and doesn't have a lock bit since haswell.
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 16: /* : * 16.6 System Agent Configuration Locking : * "5th Generation Intel Core Processor Family BIOS Specification" : * Document Number 535094 : * Revision 2.2.0, August 2014 : */
To be helpful, this needs additional comments when and why we deviate from […]
Agreed.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
This register was dropped from the lockdown sequence and doesn't have a lock bit since haswell.
Oh, how could I miss the change in the commit message. Hmmm, is this confirmed by refcode? Is it not writeable?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
Oh, how could I miss the change in the commit message. Hmmm, is this […]
Reference code doesn't have this lock bit, and the register changed quite a bit since Sandy Bridge. On Haswell with vendor firmware: 0x5f00: 0x00002707
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
Reference code doesn't have this lock bit, and the register changed quite a bit since Sandy Bridge. […]
Checked on Asrock B85M Pro4 with coreboot (which explicitly sets bit 31 of this register), and the register value is the same, so bit 31 can't be written.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 29: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
Checked on Asrock B85M Pro4 with coreboot (which explicitly sets bit 31 of this register), and the r […]
Ack
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 16: /* : * 16.6 System Agent Configuration Locking : * "5th Generation Intel Core Processor Family BIOS Specification" : * Document Number 535094 : * Revision 2.2.0, August 2014 : */
Agreed.
Alternatively we could follow the manual wrt. the order. I don't think it's that bad?
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46324
to look at the new patch set (#7).
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
The MC_LOCK register was written twice and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted by type.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 20 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/7
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46324
to look at the new patch set (#9).
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
Some registers were written to twice, and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted in ascending order for the sake of clarity.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/9
Hello build bot (Jenkins), Matt DeVillier, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46324
to look at the new patch set (#10).
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
The MC_LOCK register was written twice and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted by type.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/finalize.c 1 file changed, 20 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/10
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 10: Code-Review+2
(3 comments)
TBH, it's a mess. I don't understand the reasons to not follow the order of the spec. The added comment makes a few things better, others worse, IMHO. But this review is too annoying and I don't see it breaking anything. I'll not look into it again.
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... PS6, Line 16: /* : * 16.6 System Agent Configuration Locking : * "5th Generation Intel Core Processor Family BIOS Specification" : * Document Number 535094 : * Revision 2.2.0, August 2014 : */
Alternatively we could follow the manual wrt. the order. I don't think it's […]
Done
https://review.coreboot.org/c/coreboot/+/46324/10/src/soc/intel/broadwell/fi... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/10/src/soc/intel/broadwell/fi... PS10, Line 37: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ It's actually not literally what the spec says. We're supposed to set bits 7..0, so should `& ~0xff` first. But let's ignore that for now, as it was like this already.
https://review.coreboot.org/c/coreboot/+/46324/10/src/soc/intel/broadwell/fi... PS10, Line 39: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), /* DDR PTM */ Not covered by the comment above this function, AFAICS.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
soc/intel/broadwell: Revise SA lockdown sequence
The MC_LOCK register was written twice and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted by type.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46324 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/finalize.c 1 file changed, 20 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 300301b..ce8ab37 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -13,6 +13,15 @@ #include <soc/systemagent.h> #include <southbridge/intel/common/spi.h>
+/* + * 16.6 System Agent Configuration Locking + * "5th Generation Intel Core Processor Family BIOS Specification" + * Document Number 535094 + * Revision 2.2.0, August 2014 + * + * To ease reading, first lock PCI registers, then MCHBAR registers. + * Write the MC Lock register first, since more than one bit gets set. + */ const struct reg_script system_agent_finalize_script[] = { REG_PCI_OR16(0x50, 1 << 0), /* GGC */ REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ @@ -25,17 +34,15 @@ REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), /* DDR PTM */ REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), - REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
REG_SCRIPT_END }; @@ -76,16 +83,18 @@
reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
+ /* Read+Write the following registers */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); + spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */ RCBA32_OR(0x3a6c, 0x00000001);
- /* Read+Write the following registers */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + /* Read+Write the following register */ RCBA32(0x21a4) = RCBA32(0x21a4);
/* Indicate finalize step with post code */
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Nico Huber (Code Review)