build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63363 )
Change subject: soc/intel/meteorlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145361): https://review.coreboot.org/c/coreboot/+/63363/comment/8d9c1ad8_efc14a3f PS1, Line 31: static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145361): https://review.coreboot.org/c/coreboot/+/63363/comment/4e8f4a16_4d524400 PS1, Line 229: trailing whitespace