Change in coreboot[master]: soc/intel/common/block/gspi: set cs polarity before using

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/25013

Change subject: soc/intel/common/block/gspi: set cs polarity before using
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soc/intel/common/block/gspi: set cs polarity before using

Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly.  Failure to do so confuses cr50.

BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.

Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/25013/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 2f574a4..60c7391 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -414,9 +414,6 @@
    /* Take controller out of reset, keeping DMA in reset. */
    gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);

-	/* De-assert chip select. */
-	__gspi_cs_change(p, CS_DEASSERT);
-
    /*
     * CS control:
     * - Set SW mode.
@@ -430,6 +427,9 @@
    cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT);
    gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);

+	/* De-assert chip select. */
+	__gspi_cs_change(p, CS_DEASSERT);
+
    /* Disable SPI controller. */
    gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);