Zhongze Hu has uploaded this change for review. ( https://review.coreboot.org/25258
Change subject: mb/google/fizz: Enable I2C bus 2 ......................................................................
mb/google/fizz: Enable I2C bus 2
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase it was idle.
Google CFM add-in card is going to use this I2C bus so it needs to be re-enabled.
BUG=b:73006317 TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is working properly.
Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25258/1
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index e7654cf..2b87e31 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -296,9 +296,9 @@
# Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, @@ -329,9 +329,9 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 off end # I2C #0 + device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 + device pci 15.2 on end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2
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Zhongze Hu (Code Review)