[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support

[Jonathan Zhang (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Chu.

Jonathan Zhang has uploaded a new patch set (#11) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 )

Change subject: mb/intel: add ArcherCity CRB support
......................................................................

mb/intel: add ArcherCity CRB support

Intel ArcherCity CRB is a dual socket CRB with Intel
Sapphire Rapids Scalable Processor chipset. The chipset
also includes EmmitsBurg PCH.

Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17
Signed-off-by: Jonathan Zhang 
Signed-off-by: Johnny Lin 
---
A src/mainboard/intel/archercity_crb/Kconfig
A src/mainboard/intel/archercity_crb/Kconfig.name
A src/mainboard/intel/archercity_crb/Makefile.inc
A src/mainboard/intel/archercity_crb/acpi/platform.asl
A src/mainboard/intel/archercity_crb/board.fmd
A src/mainboard/intel/archercity_crb/board_info.txt
A src/mainboard/intel/archercity_crb/bootblock.c
A src/mainboard/intel/archercity_crb/devicetree.cb
A src/mainboard/intel/archercity_crb/dsdt.asl
A src/mainboard/intel/archercity_crb/include/mainboard_ras.h
A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h
A src/mainboard/intel/archercity_crb/ramstage.c
A src/mainboard/intel/archercity_crb/romstage.c
13 files changed, 902 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/11