Change in coreboot[master]: [WIP, TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux)

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21212

Change subject: [WIP,TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux)
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[WIP,TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux)

Change-Id: I8067080ce7c3f080ad9ebcbb27086f8a048aff6b
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/g41c-gs/romstage.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21212/1

diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index dd885db..cdefeaa 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -77,6 +77,22 @@
    		| KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 }

+static void setup_misc_rcba(void)
+{
+	RCBA32(0x88) = 0x0011d000;
+	RCBA32(0x1fc) = 0x0000060f;
+	RCBA32(0x1f4) = 0x86000040;
+	RCBA32(0x214) = 0x10030509;
+	RCBA32(0x218) = 0x00020504;
+	RCBA32(0x220) = 0x000000c5;
+	RCBA32(0x3430) = 0x00000001;
+	RCBA32(0x2027) = 0x38f6a70d;
+	RCBA16(0x3e08) = 0x0080;
+	RCBA16(0x3e48) = 0x0080;
+	RCBA32(0x3e0e) = 0x00000080;
+	RCBA32(0x3e4e) = 0x00000080;
+}
+
 void mainboard_romstage_entry(unsigned long bist)
 {
    //                          ch0      ch1
@@ -102,6 +118,8 @@

x4x_early_init();

+	setup_misc_rcba();
+
    s3_resume = southbridge_detect_s3_resume();
    if (s3_resume)
    	boot_path = BOOT_PATH_RESUME;