[XS] Change in coreboot[main]: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85028?usp=email )

Change subject: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
......................................................................

soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config

This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs
(ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type
for the RAMTOP range.

Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was
crucial to ensure data consistency, as WB caches both reads and writes.
However, since the RAMTOP range now relies on WC MTRR, the role of
CLFLUSH becomes less critical.

Removing CLFLUSH in this scenario can improve performance, as it avoids
unnecessary cache invalidations.

BUG=b:373290479
TEST=Able to build and boot google/trulo.

Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/pantherlake/Kconfig
3 files changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85028/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index dddf71f..f6e9182 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -96,7 +96,6 @@
    select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N
    select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE
    select VBOOT_LIB
-	select X86_CLFLUSH_CAR
    help
      Intel Alderlake support. Mainboards should specify the PCH
      type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 4dc6082..73d68df 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -102,7 +102,6 @@
    select TSC_MONOTONIC_TIMER
    select UDELAY_TSC
    select UDK_202302_BINDING
-	select X86_CLFLUSH_CAR
    select X86_INIT_NEED_1_SIPI
    select INTEL_KEYLOCKER
    help
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 76a84cd..96324b7 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -105,7 +105,6 @@
    select UDELAY_TSC
    select UDK_202302_BINDING
    select USE_X86_64_SUPPORT
-	select X86_CLFLUSH_CAR
    select X86_INIT_NEED_1_SIPI
    help
      Intel Pantherlake support. Mainboards should specify the SoC