[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81377?usp=email )

Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
......................................................................

soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation

Domain SSDT is dyanmically generated by soc_pci_domain_fill_ssdt.
_STA, _PXM and _PRT is yet to be added back.

TEST=intel/archercity CRB

Linux ACPI host bridge parsing logs are kept the same before and
after, with some minor issue fixed.

Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba
Signed-off-by: Shuo Liu 
---
M src/mainboard/intel/archercity_crb/dsdt.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
M src/soc/intel/xeon_sp/spr/soc_acpi.c
3 files changed, 77 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/1

diff --git a/src/mainboard/intel/archercity_crb/dsdt.asl b/src/mainboard/intel/archercity_crb/dsdt.asl
index 2204748..45842e58 100644
--- a/src/mainboard/intel/archercity_crb/dsdt.asl
+++ b/src/mainboard/intel/archercity_crb/dsdt.asl
@@ -10,6 +10,16 @@
    0x20110725	// OEM revision
 )
 {
+	Scope (_SB)
+	{
+		Device(PC00)
+		{
+			Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)
+			Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)
+			Name (_UID, "PC00")
+		}
+	}
+
    #include <acpi/dsdt_top.asl>
    // platform ACPI tables
    #include "acpi/platform.asl"
diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
index c1b8bdc..a1e1bba 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
@@ -10,10 +10,6 @@
 {
    #include "uncore_irq.asl"

-	#define SOCKET 0
-	#include "iiostack.asl"
-	#undef SOCKET
-
    #if CONFIG(SOC_ACPI_HEST)
    	Method (_OSC, 4, NotSerialized)
    	{
@@ -22,22 +18,4 @@
    		Return (Arg3)
    	}
    #endif
-
-	#if (CONFIG_MAX_SOCKET > 1)
-		#define SOCKET 1
-		#include "iiostack.asl"
-		#undef SOCKET
-	#endif
-
-	#if (CONFIG_MAX_SOCKET > 2)
-		#define SOCKET 2
-		#include "iiostack.asl"
-		#undef SOCKET
-	#endif
-
-	#if (CONFIG_MAX_SOCKET > 3)
-		#define SOCKET 3
-		#include "iiostack.asl"
-		#undef SOCKET
-	#endif
 }
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index 607ee6c..9425d64 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
 #include <arch/smp/mpspec.h>
 #include <arch/vga.h>
 #include <assert.h>
@@ -12,6 +13,7 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
 #include <soc/acpi.h>
+#include <soc/chip_common.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -215,3 +217,68 @@

return current;
 }
+
+void soc_pci_domain_fill_ssdt(const struct device *domain)
+{
+	const char *name = acpi_device_name(domain);
+	printk(BIOS_DEBUG, "%s: Creating device %s\n", __func__, name);
+
+	if (!is_domain0(domain)) {
+	/*
+	 * Scope (_SB) {
+	 *      Device (name) {
+	 */
+		acpigen_write_scope("\_SB");
+		acpigen_write_device(name);
+
+	/*
+	 *		Name (_HID, EisaId ("PNP0A08"))
+	 *		Name (_CID, EisaId ("PNP0A03"))
+	 *		Name (_UID, name)
+	 */
+		acpigen_write_name("_HID");
+		acpigen_emit_eisaid("PNP0A08");
+		acpigen_write_name("_CID");
+		acpigen_emit_eisaid("PNP0A03");
+		acpigen_write_name("_UID");
+		acpigen_write_string(name);
+
+	/*
+	 *	} //Device
+	 * } //Scope
+	 */
+		acpigen_pop_len();
+		acpigen_pop_len();
+	}
+
+	/*
+	 * Scope (acpi_device_path(domain)) {
+	 */
+	acpigen_write_scope(acpi_device_path(domain));
+
+	/*
+	 *              Method (_OSC, 4, NotSerialized)
+	 *              {
+	 */
+	soc_acpigen_write_OSC(domain);
+	/*
+	 *              }
+	 */
+
+	/*
+	 * | //Scope
+	 */
+	acpigen_pop_len();
+
+        return;
+}
+
+unsigned long get_supported_pci_host_bridge_features(const struct device *domain)
+{
+	return 0;
+}
+
+unsigned long get_supported_cxl_host_bridge_features(const struct device *domain)
+{
+	return 0;
+}