Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31376
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
mb/google/hatch: Bump up the BIOS region to 28MiB
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/chromeos.fmd 1 file changed, 19 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31376/1
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 25d579b..e000793 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -3,34 +3,37 @@ SI_DESC@0x0 0x1000 SI_ME@0x1000 0x3ff000 } - SI_BIOS@0x1400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 } - RW_SECTION_B@0x2d0000 0x2d0000 { + RW_SECTION_B@0x13e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { + RW_ELOG@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 + RW_VPD@0x38000 0x2000 + RW_NVRAM@0x3a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x800000 0x400000 { + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... File src/mainboard/google/hatch/chromeos.fmd:
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... PS1, Line 18: 3cffc0 this size increase is almost 1MB, I think it will impact the time for FW hashing.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... File src/mainboard/google/hatch/chromeos.fmd:
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... PS1, Line 18: 3cffc0
this size increase is almost 1MB, I think it will impact the time for FW hashing.
Currently, I see a boot time impact of ~300usec in vboot verification because of this change.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... File src/mainboard/google/hatch/chromeos.fmd:
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... PS1, Line 18: 3cffc0
Currently, I see a boot time impact of ~300usec in vboot verification because of this change.
We do not hash the entire cbfs region. The vblock carries the size of the region we signature check.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1: Code-Review+2
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... File src/mainboard/google/hatch/chromeos.fmd:
https://review.coreboot.org/#/c/31376/1/src/mainboard/google/hatch/chromeos.... PS1, Line 18: 3cffc0
We do not hash the entire cbfs region. The vblock carries the size of the region we signature check.
Understood.
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31376 )
Change subject: mb/google/hatch: Bump up the BIOS region to 28MiB ......................................................................
mb/google/hatch: Bump up the BIOS region to 28MiB
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/31376 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/chromeos.fmd 1 file changed, 19 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Rizwan Qureshi: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 25d579b..e000793 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -3,34 +3,37 @@ SI_DESC@0x0 0x1000 SI_ME@0x1000 0x3ff000 } - SI_BIOS@0x1400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 } - RW_SECTION_B@0x2d0000 0x2d0000 { + RW_SECTION_B@0x13e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { + RW_ELOG@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 + RW_VPD@0x38000 0x2000 + RW_NVRAM@0x3a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x800000 0x400000 { + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800
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Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Rizwan Qureshi (Code Review)