New patch to review for coreboot: b6fe0df No need to specify '1' in define of header guard
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8103
-gerrit
commit b6fe0dfb02ce5bf6f3526e6d0d63994360dd1d11 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Tue Jan 6 02:48:57 2015 +1100
No need to specify '1' in define of header guard
Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ++-- src/northbridge/intel/gm45/delay.h | 4 ++-- src/northbridge/intel/gm45/gm45.h | 4 ++-- src/northbridge/intel/haswell/haswell.h | 4 ++-- src/northbridge/intel/nehalem/gma.h | 4 ++-- src/northbridge/intel/nehalem/nehalem.h | 4 ++-- src/northbridge/intel/sandybridge/sandybridge.h | 4 ++-- src/northbridge/intel/sch/sch.h | 4 ++-- 9 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index abce07a..dab5a9c 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index 9a0cf42..d67d696 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -20,7 +20,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
/* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h index dda6cf4..a28a3f1 100644 --- a/src/northbridge/intel/gm45/delay.h +++ b/src/northbridge/intel/gm45/delay.h @@ -18,11 +18,11 @@ */
#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ -#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__
#include <delay.h>
void ns100delay(u32); void udelay_from_reset(u32);
-#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 673160b..5bdf9e4 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -19,7 +19,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_GM45_H__
#include "southbridge/intel/i82801ix/i82801ix.h"
@@ -434,4 +434,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); #endif
-#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 55f6f28..d8221a9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -19,7 +19,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ -#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1 +#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
/* Chipset types */ #define HASWELL_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index f0e1c53..baf12f2 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -19,7 +19,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
/* mailbox 0: header */ typedef struct { @@ -118,4 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t;
-#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 60cafdf..73137b2 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -20,7 +20,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
#ifndef __ASSEMBLER__
@@ -623,4 +623,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d38bf0b..0790ae8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -19,7 +19,7 @@ */
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
/* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -240,4 +240,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 5700842..3eb0825 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -20,7 +20,7 @@ */
#ifndef __SCH_PULSBO_H__ -#define __SCH_PULSBO_H__ 1 +#define __SCH_PULSBO_H__
int sch_port_access_read(int port, int reg, int bytes); void sch_port_access_write(int port, int reg, int bytes, long data); @@ -51,4 +51,4 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); /* FIXME: should probably be in southbridge, but is setup in romstage, too */ #define CMC_SHADOW 0x3faf0000
-#endif +#endif /* __SCH_PULSBO_H__ */
-
Edward O'Callaghan