Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32266
Change subject: mb/google/hatch: Update sleep signal assertion widths ......................................................................
mb/google/hatch: Update sleep signal assertion widths
Based on the power rail discharge times measured on hatch, update the assertions widths that have to be programmed in SoC.
BUG=b:129328209 TEST=warm/cold reboot and S3 are working fine on hatch.
Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32266/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7dd41a2..e39f140 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,11 @@ # Unlock GPIO pads register "PchUnlockGpioPads" = "1"
+ register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32266 )
Change subject: mb/google/hatch: Update sleep signal assertion widths ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32266 )
Change subject: mb/google/hatch: Update sleep signal assertion widths ......................................................................
mb/google/hatch: Update sleep signal assertion widths
Based on the power rail discharge times measured on hatch, update the assertions widths that have to be programmed in SoC.
BUG=b:129328209 TEST=warm/cold reboot and S3 are working fine on hatch.
Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7dd41a2..e39f140 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,11 @@ # Unlock GPIO pads register "PchUnlockGpioPads" = "1"
+ register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
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Furquan Shaikh (Code Review) -
Rizwan Qureshi (Code Review)
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Subrata Banik (Code Review)