Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )

Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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Patch Set 12:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39538/12//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39538/12//COMMIT_MSG@11 
PS12, Line 11: PcieRpL1Substates to devicetree to allow boards to set these options.
> From Fsp.bsf: […]

Thanks.

https://review.coreboot.org/c/coreboot/+/39538/12/src/soc/intel/skylake/chip... 
File src/soc/intel/skylake/chip.c:

https://review.coreboot.org/c/coreboot/+/39538/12/src/soc/intel/skylake/chip... 
PS12, Line 136: mainboard
mainboards