[XS] Change in coreboot[main]: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET

[Subrata Banik (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Rizwan Qureshi, Tarun.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78054?usp=email )

Change subject: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
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Patch Set 3:

(1 comment)

File src/soc/intel/meteorlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/78054/comment/322128e4_b379827f :
PS3, Line 442: # The default offset to store CSE RW FW version information is at 68. In Intel Meteor Lake based
             : # systems that use PSR, the additional size required to keep CSE RW FW version information and
             : # PSR back-up status in adjacent CMOS memory at offset 68 is not available. Offset 161 has
             : # enough space to keep both the CSE related information together. Hence override the default
             : # offset to 161.
```

# The default offset to store CSE RW FW version information is at 68.
# However, in Intel Meteor Lake based systems that use PSR, the additional
# size required to keep CSE RW FW version information and PSR back-up status
# in adjacent CMOS memory at offset 68 is not available. Therefore, we
# override the default offset to 161, which has enough space to keep both
# the CSE related information together.
```